1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Interconnect framework driver for i.MX SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2019-2020, NXP 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DT_BINDINGS_INTERCONNECT_IMX8MN_H 9*4882a593Smuzhiyun #define __DT_BINDINGS_INTERCONNECT_IMX8MN_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define IMX8MN_ICN_NOC 1 12*4882a593Smuzhiyun #define IMX8MN_ICS_DRAM 2 13*4882a593Smuzhiyun #define IMX8MN_ICS_OCRAM 3 14*4882a593Smuzhiyun #define IMX8MN_ICM_A53 4 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define IMX8MN_ICM_GPU 5 17*4882a593Smuzhiyun #define IMX8MN_ICN_GPU 6 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define IMX8MN_ICM_CSI1 7 20*4882a593Smuzhiyun #define IMX8MN_ICM_CSI2 8 21*4882a593Smuzhiyun #define IMX8MN_ICM_ISI 9 22*4882a593Smuzhiyun #define IMX8MN_ICM_LCDIF 10 23*4882a593Smuzhiyun #define IMX8MN_ICN_MIPI 11 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define IMX8MN_ICM_USB 12 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define IMX8MN_ICM_SDMA2 13 28*4882a593Smuzhiyun #define IMX8MN_ICM_SDMA3 14 29*4882a593Smuzhiyun #define IMX8MN_ICN_AUDIO 15 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define IMX8MN_ICN_ENET 16 32*4882a593Smuzhiyun #define IMX8MN_ICM_ENET 17 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define IMX8MN_ICM_NAND 18 35*4882a593Smuzhiyun #define IMX8MN_ICM_SDMA1 19 36*4882a593Smuzhiyun #define IMX8MN_ICM_USDHC1 20 37*4882a593Smuzhiyun #define IMX8MN_ICM_USDHC2 21 38*4882a593Smuzhiyun #define IMX8MN_ICM_USDHC3 22 39*4882a593Smuzhiyun #define IMX8MN_ICN_MAIN 23 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif /* __DT_BINDINGS_INTERCONNECT_IMX8MN_H */ 42