1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_QCOM_SPMI_VADC_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* Voltage ADC channels */ 10*4882a593Smuzhiyun #define VADC_USBIN 0x00 11*4882a593Smuzhiyun #define VADC_DCIN 0x01 12*4882a593Smuzhiyun #define VADC_VCHG_SNS 0x02 13*4882a593Smuzhiyun #define VADC_SPARE1_03 0x03 14*4882a593Smuzhiyun #define VADC_USB_ID_MV 0x04 15*4882a593Smuzhiyun #define VADC_VCOIN 0x05 16*4882a593Smuzhiyun #define VADC_VBAT_SNS 0x06 17*4882a593Smuzhiyun #define VADC_VSYS 0x07 18*4882a593Smuzhiyun #define VADC_DIE_TEMP 0x08 19*4882a593Smuzhiyun #define VADC_REF_625MV 0x09 20*4882a593Smuzhiyun #define VADC_REF_1250MV 0x0a 21*4882a593Smuzhiyun #define VADC_CHG_TEMP 0x0b 22*4882a593Smuzhiyun #define VADC_SPARE1 0x0c 23*4882a593Smuzhiyun #define VADC_SPARE2 0x0d 24*4882a593Smuzhiyun #define VADC_GND_REF 0x0e 25*4882a593Smuzhiyun #define VADC_VDD_VADC 0x0f 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define VADC_P_MUX1_1_1 0x10 28*4882a593Smuzhiyun #define VADC_P_MUX2_1_1 0x11 29*4882a593Smuzhiyun #define VADC_P_MUX3_1_1 0x12 30*4882a593Smuzhiyun #define VADC_P_MUX4_1_1 0x13 31*4882a593Smuzhiyun #define VADC_P_MUX5_1_1 0x14 32*4882a593Smuzhiyun #define VADC_P_MUX6_1_1 0x15 33*4882a593Smuzhiyun #define VADC_P_MUX7_1_1 0x16 34*4882a593Smuzhiyun #define VADC_P_MUX8_1_1 0x17 35*4882a593Smuzhiyun #define VADC_P_MUX9_1_1 0x18 36*4882a593Smuzhiyun #define VADC_P_MUX10_1_1 0x19 37*4882a593Smuzhiyun #define VADC_P_MUX11_1_1 0x1a 38*4882a593Smuzhiyun #define VADC_P_MUX12_1_1 0x1b 39*4882a593Smuzhiyun #define VADC_P_MUX13_1_1 0x1c 40*4882a593Smuzhiyun #define VADC_P_MUX14_1_1 0x1d 41*4882a593Smuzhiyun #define VADC_P_MUX15_1_1 0x1e 42*4882a593Smuzhiyun #define VADC_P_MUX16_1_1 0x1f 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define VADC_P_MUX1_1_3 0x20 45*4882a593Smuzhiyun #define VADC_P_MUX2_1_3 0x21 46*4882a593Smuzhiyun #define VADC_P_MUX3_1_3 0x22 47*4882a593Smuzhiyun #define VADC_P_MUX4_1_3 0x23 48*4882a593Smuzhiyun #define VADC_P_MUX5_1_3 0x24 49*4882a593Smuzhiyun #define VADC_P_MUX6_1_3 0x25 50*4882a593Smuzhiyun #define VADC_P_MUX7_1_3 0x26 51*4882a593Smuzhiyun #define VADC_P_MUX8_1_3 0x27 52*4882a593Smuzhiyun #define VADC_P_MUX9_1_3 0x28 53*4882a593Smuzhiyun #define VADC_P_MUX10_1_3 0x29 54*4882a593Smuzhiyun #define VADC_P_MUX11_1_3 0x2a 55*4882a593Smuzhiyun #define VADC_P_MUX12_1_3 0x2b 56*4882a593Smuzhiyun #define VADC_P_MUX13_1_3 0x2c 57*4882a593Smuzhiyun #define VADC_P_MUX14_1_3 0x2d 58*4882a593Smuzhiyun #define VADC_P_MUX15_1_3 0x2e 59*4882a593Smuzhiyun #define VADC_P_MUX16_1_3 0x2f 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define VADC_LR_MUX1_BAT_THERM 0x30 62*4882a593Smuzhiyun #define VADC_LR_MUX2_BAT_ID 0x31 63*4882a593Smuzhiyun #define VADC_LR_MUX3_XO_THERM 0x32 64*4882a593Smuzhiyun #define VADC_LR_MUX4_AMUX_THM1 0x33 65*4882a593Smuzhiyun #define VADC_LR_MUX5_AMUX_THM2 0x34 66*4882a593Smuzhiyun #define VADC_LR_MUX6_AMUX_THM3 0x35 67*4882a593Smuzhiyun #define VADC_LR_MUX7_HW_ID 0x36 68*4882a593Smuzhiyun #define VADC_LR_MUX8_AMUX_THM4 0x37 69*4882a593Smuzhiyun #define VADC_LR_MUX9_AMUX_THM5 0x38 70*4882a593Smuzhiyun #define VADC_LR_MUX10_USB_ID 0x39 71*4882a593Smuzhiyun #define VADC_AMUX_PU1 0x3a 72*4882a593Smuzhiyun #define VADC_AMUX_PU2 0x3b 73*4882a593Smuzhiyun #define VADC_LR_MUX3_BUF_XO_THERM 0x3c 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define VADC_LR_MUX1_PU1_BAT_THERM 0x70 76*4882a593Smuzhiyun #define VADC_LR_MUX2_PU1_BAT_ID 0x71 77*4882a593Smuzhiyun #define VADC_LR_MUX3_PU1_XO_THERM 0x72 78*4882a593Smuzhiyun #define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 79*4882a593Smuzhiyun #define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 80*4882a593Smuzhiyun #define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 81*4882a593Smuzhiyun #define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 82*4882a593Smuzhiyun #define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 83*4882a593Smuzhiyun #define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 84*4882a593Smuzhiyun #define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 85*4882a593Smuzhiyun #define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 88*4882a593Smuzhiyun #define VADC_LR_MUX2_PU2_BAT_ID 0xb1 89*4882a593Smuzhiyun #define VADC_LR_MUX3_PU2_XO_THERM 0xb2 90*4882a593Smuzhiyun #define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 91*4882a593Smuzhiyun #define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 92*4882a593Smuzhiyun #define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 93*4882a593Smuzhiyun #define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 94*4882a593Smuzhiyun #define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 95*4882a593Smuzhiyun #define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 96*4882a593Smuzhiyun #define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 97*4882a593Smuzhiyun #define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 100*4882a593Smuzhiyun #define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 101*4882a593Smuzhiyun #define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 102*4882a593Smuzhiyun #define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 103*4882a593Smuzhiyun #define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 104*4882a593Smuzhiyun #define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 105*4882a593Smuzhiyun #define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 106*4882a593Smuzhiyun #define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 107*4882a593Smuzhiyun #define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 108*4882a593Smuzhiyun #define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 109*4882a593Smuzhiyun #define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* ADC channels for SPMI PMIC5 */ 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define ADC5_REF_GND 0x00 114*4882a593Smuzhiyun #define ADC5_1P25VREF 0x01 115*4882a593Smuzhiyun #define ADC5_VREF_VADC 0x02 116*4882a593Smuzhiyun #define ADC5_VREF_VADC5_DIV_3 0x82 117*4882a593Smuzhiyun #define ADC5_VPH_PWR 0x83 118*4882a593Smuzhiyun #define ADC5_VBAT_SNS 0x84 119*4882a593Smuzhiyun #define ADC5_VCOIN 0x85 120*4882a593Smuzhiyun #define ADC5_DIE_TEMP 0x06 121*4882a593Smuzhiyun #define ADC5_USB_IN_I 0x07 122*4882a593Smuzhiyun #define ADC5_USB_IN_V_16 0x08 123*4882a593Smuzhiyun #define ADC5_CHG_TEMP 0x09 124*4882a593Smuzhiyun #define ADC5_BAT_THERM 0x0a 125*4882a593Smuzhiyun #define ADC5_BAT_ID 0x0b 126*4882a593Smuzhiyun #define ADC5_XO_THERM 0x0c 127*4882a593Smuzhiyun #define ADC5_AMUX_THM1 0x0d 128*4882a593Smuzhiyun #define ADC5_AMUX_THM2 0x0e 129*4882a593Smuzhiyun #define ADC5_AMUX_THM3 0x0f 130*4882a593Smuzhiyun #define ADC5_AMUX_THM4 0x10 131*4882a593Smuzhiyun #define ADC5_AMUX_THM5 0x11 132*4882a593Smuzhiyun #define ADC5_GPIO1 0x12 133*4882a593Smuzhiyun #define ADC5_GPIO2 0x13 134*4882a593Smuzhiyun #define ADC5_GPIO3 0x14 135*4882a593Smuzhiyun #define ADC5_GPIO4 0x15 136*4882a593Smuzhiyun #define ADC5_GPIO5 0x16 137*4882a593Smuzhiyun #define ADC5_GPIO6 0x17 138*4882a593Smuzhiyun #define ADC5_GPIO7 0x18 139*4882a593Smuzhiyun #define ADC5_SBUx 0x99 140*4882a593Smuzhiyun #define ADC5_MID_CHG_DIV6 0x1e 141*4882a593Smuzhiyun #define ADC5_OFF 0xff 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* 30k pull-up1 */ 144*4882a593Smuzhiyun #define ADC5_BAT_THERM_30K_PU 0x2a 145*4882a593Smuzhiyun #define ADC5_BAT_ID_30K_PU 0x2b 146*4882a593Smuzhiyun #define ADC5_XO_THERM_30K_PU 0x2c 147*4882a593Smuzhiyun #define ADC5_AMUX_THM1_30K_PU 0x2d 148*4882a593Smuzhiyun #define ADC5_AMUX_THM2_30K_PU 0x2e 149*4882a593Smuzhiyun #define ADC5_AMUX_THM3_30K_PU 0x2f 150*4882a593Smuzhiyun #define ADC5_AMUX_THM4_30K_PU 0x30 151*4882a593Smuzhiyun #define ADC5_AMUX_THM5_30K_PU 0x31 152*4882a593Smuzhiyun #define ADC5_GPIO1_30K_PU 0x32 153*4882a593Smuzhiyun #define ADC5_GPIO2_30K_PU 0x33 154*4882a593Smuzhiyun #define ADC5_GPIO3_30K_PU 0x34 155*4882a593Smuzhiyun #define ADC5_GPIO4_30K_PU 0x35 156*4882a593Smuzhiyun #define ADC5_GPIO5_30K_PU 0x36 157*4882a593Smuzhiyun #define ADC5_GPIO6_30K_PU 0x37 158*4882a593Smuzhiyun #define ADC5_GPIO7_30K_PU 0x38 159*4882a593Smuzhiyun #define ADC5_SBUx_30K_PU 0x39 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* 100k pull-up2 */ 162*4882a593Smuzhiyun #define ADC5_BAT_THERM_100K_PU 0x4a 163*4882a593Smuzhiyun #define ADC5_BAT_ID_100K_PU 0x4b 164*4882a593Smuzhiyun #define ADC5_XO_THERM_100K_PU 0x4c 165*4882a593Smuzhiyun #define ADC5_AMUX_THM1_100K_PU 0x4d 166*4882a593Smuzhiyun #define ADC5_AMUX_THM2_100K_PU 0x4e 167*4882a593Smuzhiyun #define ADC5_AMUX_THM3_100K_PU 0x4f 168*4882a593Smuzhiyun #define ADC5_AMUX_THM4_100K_PU 0x50 169*4882a593Smuzhiyun #define ADC5_AMUX_THM5_100K_PU 0x51 170*4882a593Smuzhiyun #define ADC5_GPIO1_100K_PU 0x52 171*4882a593Smuzhiyun #define ADC5_GPIO2_100K_PU 0x53 172*4882a593Smuzhiyun #define ADC5_GPIO3_100K_PU 0x54 173*4882a593Smuzhiyun #define ADC5_GPIO4_100K_PU 0x55 174*4882a593Smuzhiyun #define ADC5_GPIO5_100K_PU 0x56 175*4882a593Smuzhiyun #define ADC5_GPIO6_100K_PU 0x57 176*4882a593Smuzhiyun #define ADC5_GPIO7_100K_PU 0x58 177*4882a593Smuzhiyun #define ADC5_SBUx_100K_PU 0x59 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* 400k pull-up3 */ 180*4882a593Smuzhiyun #define ADC5_BAT_THERM_400K_PU 0x6a 181*4882a593Smuzhiyun #define ADC5_BAT_ID_400K_PU 0x6b 182*4882a593Smuzhiyun #define ADC5_XO_THERM_400K_PU 0x6c 183*4882a593Smuzhiyun #define ADC5_AMUX_THM1_400K_PU 0x6d 184*4882a593Smuzhiyun #define ADC5_AMUX_THM2_400K_PU 0x6e 185*4882a593Smuzhiyun #define ADC5_AMUX_THM3_400K_PU 0x6f 186*4882a593Smuzhiyun #define ADC5_AMUX_THM4_400K_PU 0x70 187*4882a593Smuzhiyun #define ADC5_AMUX_THM5_400K_PU 0x71 188*4882a593Smuzhiyun #define ADC5_GPIO1_400K_PU 0x72 189*4882a593Smuzhiyun #define ADC5_GPIO2_400K_PU 0x73 190*4882a593Smuzhiyun #define ADC5_GPIO3_400K_PU 0x74 191*4882a593Smuzhiyun #define ADC5_GPIO4_400K_PU 0x75 192*4882a593Smuzhiyun #define ADC5_GPIO5_400K_PU 0x76 193*4882a593Smuzhiyun #define ADC5_GPIO6_400K_PU 0x77 194*4882a593Smuzhiyun #define ADC5_GPIO7_400K_PU 0x78 195*4882a593Smuzhiyun #define ADC5_SBUx_400K_PU 0x79 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun /* 1/3 Divider */ 198*4882a593Smuzhiyun #define ADC5_GPIO1_DIV3 0x92 199*4882a593Smuzhiyun #define ADC5_GPIO2_DIV3 0x93 200*4882a593Smuzhiyun #define ADC5_GPIO3_DIV3 0x94 201*4882a593Smuzhiyun #define ADC5_GPIO4_DIV3 0x95 202*4882a593Smuzhiyun #define ADC5_GPIO5_DIV3 0x96 203*4882a593Smuzhiyun #define ADC5_GPIO6_DIV3 0x97 204*4882a593Smuzhiyun #define ADC5_GPIO7_DIV3 0x98 205*4882a593Smuzhiyun #define ADC5_SBUx_DIV3 0x99 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun /* Current and combined current/voltage channels */ 208*4882a593Smuzhiyun #define ADC5_INT_EXT_ISENSE 0xa1 209*4882a593Smuzhiyun #define ADC5_PARALLEL_ISENSE 0xa5 210*4882a593Smuzhiyun #define ADC5_CUR_REPLICA_VDS 0xa7 211*4882a593Smuzhiyun #define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9 212*4882a593Smuzhiyun #define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab 213*4882a593Smuzhiyun #define ADC5_EXT_SENS_OFFSET 0xad 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun #define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0 216*4882a593Smuzhiyun #define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1 217*4882a593Smuzhiyun #define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2 218*4882a593Smuzhiyun #define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3 219*4882a593Smuzhiyun #define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4 220*4882a593Smuzhiyun #define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun #define ADC5_MAX_CHANNEL 0xc0 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun /* ADC channels for ADC for PMIC7 */ 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun #define ADC7_REF_GND 0x00 227*4882a593Smuzhiyun #define ADC7_1P25VREF 0x01 228*4882a593Smuzhiyun #define ADC7_VREF_VADC 0x02 229*4882a593Smuzhiyun #define ADC7_DIE_TEMP 0x03 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #define ADC7_AMUX_THM1 0x04 232*4882a593Smuzhiyun #define ADC7_AMUX_THM2 0x05 233*4882a593Smuzhiyun #define ADC7_AMUX_THM3 0x06 234*4882a593Smuzhiyun #define ADC7_AMUX_THM4 0x07 235*4882a593Smuzhiyun #define ADC7_AMUX_THM5 0x08 236*4882a593Smuzhiyun #define ADC7_AMUX_THM6 0x09 237*4882a593Smuzhiyun #define ADC7_GPIO1 0x0a 238*4882a593Smuzhiyun #define ADC7_GPIO2 0x0b 239*4882a593Smuzhiyun #define ADC7_GPIO3 0x0c 240*4882a593Smuzhiyun #define ADC7_GPIO4 0x0d 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun #define ADC7_CHG_TEMP 0x10 243*4882a593Smuzhiyun #define ADC7_USB_IN_V_16 0x11 244*4882a593Smuzhiyun #define ADC7_VDC_16 0x12 245*4882a593Smuzhiyun #define ADC7_CC1_ID 0x13 246*4882a593Smuzhiyun #define ADC7_VREF_BAT_THERM 0x15 247*4882a593Smuzhiyun #define ADC7_IIN_FB 0x17 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun /* 30k pull-up1 */ 250*4882a593Smuzhiyun #define ADC7_AMUX_THM1_30K_PU 0x24 251*4882a593Smuzhiyun #define ADC7_AMUX_THM2_30K_PU 0x25 252*4882a593Smuzhiyun #define ADC7_AMUX_THM3_30K_PU 0x26 253*4882a593Smuzhiyun #define ADC7_AMUX_THM4_30K_PU 0x27 254*4882a593Smuzhiyun #define ADC7_AMUX_THM5_30K_PU 0x28 255*4882a593Smuzhiyun #define ADC7_AMUX_THM6_30K_PU 0x29 256*4882a593Smuzhiyun #define ADC7_GPIO1_30K_PU 0x2a 257*4882a593Smuzhiyun #define ADC7_GPIO2_30K_PU 0x2b 258*4882a593Smuzhiyun #define ADC7_GPIO3_30K_PU 0x2c 259*4882a593Smuzhiyun #define ADC7_GPIO4_30K_PU 0x2d 260*4882a593Smuzhiyun #define ADC7_CC1_ID_30K_PU 0x33 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun /* 100k pull-up2 */ 263*4882a593Smuzhiyun #define ADC7_AMUX_THM1_100K_PU 0x44 264*4882a593Smuzhiyun #define ADC7_AMUX_THM2_100K_PU 0x45 265*4882a593Smuzhiyun #define ADC7_AMUX_THM3_100K_PU 0x46 266*4882a593Smuzhiyun #define ADC7_AMUX_THM4_100K_PU 0x47 267*4882a593Smuzhiyun #define ADC7_AMUX_THM5_100K_PU 0x48 268*4882a593Smuzhiyun #define ADC7_AMUX_THM6_100K_PU 0x49 269*4882a593Smuzhiyun #define ADC7_GPIO1_100K_PU 0x4a 270*4882a593Smuzhiyun #define ADC7_GPIO2_100K_PU 0x4b 271*4882a593Smuzhiyun #define ADC7_GPIO3_100K_PU 0x4c 272*4882a593Smuzhiyun #define ADC7_GPIO4_100K_PU 0x4d 273*4882a593Smuzhiyun #define ADC7_CC1_ID_100K_PU 0x53 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun /* 400k pull-up3 */ 276*4882a593Smuzhiyun #define ADC7_AMUX_THM1_400K_PU 0x64 277*4882a593Smuzhiyun #define ADC7_AMUX_THM2_400K_PU 0x65 278*4882a593Smuzhiyun #define ADC7_AMUX_THM3_400K_PU 0x66 279*4882a593Smuzhiyun #define ADC7_AMUX_THM4_400K_PU 0x67 280*4882a593Smuzhiyun #define ADC7_AMUX_THM5_400K_PU 0x68 281*4882a593Smuzhiyun #define ADC7_AMUX_THM6_400K_PU 0x69 282*4882a593Smuzhiyun #define ADC7_GPIO1_400K_PU 0x6a 283*4882a593Smuzhiyun #define ADC7_GPIO2_400K_PU 0x6b 284*4882a593Smuzhiyun #define ADC7_GPIO3_400K_PU 0x6c 285*4882a593Smuzhiyun #define ADC7_GPIO4_400K_PU 0x6d 286*4882a593Smuzhiyun #define ADC7_CC1_ID_400K_PU 0x73 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun /* 1/3 Divider */ 289*4882a593Smuzhiyun #define ADC7_GPIO1_DIV3 0x8a 290*4882a593Smuzhiyun #define ADC7_GPIO2_DIV3 0x8b 291*4882a593Smuzhiyun #define ADC7_GPIO3_DIV3 0x8c 292*4882a593Smuzhiyun #define ADC7_GPIO4_DIV3 0x8d 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun #define ADC7_VPH_PWR 0x8e 295*4882a593Smuzhiyun #define ADC7_VBAT_SNS 0x8f 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun #define ADC7_SBUx 0x94 298*4882a593Smuzhiyun #define ADC7_VBAT_2S_MID 0x96 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ 301