1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef PM8350_SID 10*4882a593Smuzhiyun #define PM8350_SID 1 11*4882a593Smuzhiyun #endif 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* ADC channels for PM8350_ADC for PMIC7 */ 14*4882a593Smuzhiyun #define PM8350_ADC7_REF_GND (PM8350_SID << 8 | 0x0) 15*4882a593Smuzhiyun #define PM8350_ADC7_1P25VREF (PM8350_SID << 8 | 0x01) 16*4882a593Smuzhiyun #define PM8350_ADC7_VREF_VADC (PM8350_SID << 8 | 0x02) 17*4882a593Smuzhiyun #define PM8350_ADC7_DIE_TEMP (PM8350_SID << 8 | 0x03) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM1 (PM8350_SID << 8 | 0x04) 20*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM2 (PM8350_SID << 8 | 0x05) 21*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM3 (PM8350_SID << 8 | 0x06) 22*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM4 (PM8350_SID << 8 | 0x07) 23*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM5 (PM8350_SID << 8 | 0x08) 24*4882a593Smuzhiyun #define PM8350_ADC7_GPIO1 (PM8350_SID << 8 | 0x0a) 25*4882a593Smuzhiyun #define PM8350_ADC7_GPIO2 (PM8350_SID << 8 | 0x0b) 26*4882a593Smuzhiyun #define PM8350_ADC7_GPIO3 (PM8350_SID << 8 | 0x0c) 27*4882a593Smuzhiyun #define PM8350_ADC7_GPIO4 (PM8350_SID << 8 | 0x0d) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30k pull-up1 */ 30*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM1_30K_PU (PM8350_SID << 8 | 0x24) 31*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM2_30K_PU (PM8350_SID << 8 | 0x25) 32*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM3_30K_PU (PM8350_SID << 8 | 0x26) 33*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM4_30K_PU (PM8350_SID << 8 | 0x27) 34*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM5_30K_PU (PM8350_SID << 8 | 0x28) 35*4882a593Smuzhiyun #define PM8350_ADC7_GPIO1_30K_PU (PM8350_SID << 8 | 0x2a) 36*4882a593Smuzhiyun #define PM8350_ADC7_GPIO2_30K_PU (PM8350_SID << 8 | 0x2b) 37*4882a593Smuzhiyun #define PM8350_ADC7_GPIO3_30K_PU (PM8350_SID << 8 | 0x2c) 38*4882a593Smuzhiyun #define PM8350_ADC7_GPIO4_30K_PU (PM8350_SID << 8 | 0x2d) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* 100k pull-up2 */ 41*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM1_100K_PU (PM8350_SID << 8 | 0x44) 42*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM2_100K_PU (PM8350_SID << 8 | 0x45) 43*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM3_100K_PU (PM8350_SID << 8 | 0x46) 44*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM4_100K_PU (PM8350_SID << 8 | 0x47) 45*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM5_100K_PU (PM8350_SID << 8 | 0x48) 46*4882a593Smuzhiyun #define PM8350_ADC7_GPIO1_100K_PU (PM8350_SID << 8 | 0x4a) 47*4882a593Smuzhiyun #define PM8350_ADC7_GPIO2_100K_PU (PM8350_SID << 8 | 0x4b) 48*4882a593Smuzhiyun #define PM8350_ADC7_GPIO3_100K_PU (PM8350_SID << 8 | 0x4c) 49*4882a593Smuzhiyun #define PM8350_ADC7_GPIO4_100K_PU (PM8350_SID << 8 | 0x4d) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 400k pull-up3 */ 52*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM1_400K_PU (PM8350_SID << 8 | 0x64) 53*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM2_400K_PU (PM8350_SID << 8 | 0x65) 54*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM3_400K_PU (PM8350_SID << 8 | 0x66) 55*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM4_400K_PU (PM8350_SID << 8 | 0x67) 56*4882a593Smuzhiyun #define PM8350_ADC7_AMUX_THM5_400K_PU (PM8350_SID << 8 | 0x68) 57*4882a593Smuzhiyun #define PM8350_ADC7_GPIO1_400K_PU (PM8350_SID << 8 | 0x6a) 58*4882a593Smuzhiyun #define PM8350_ADC7_GPIO2_400K_PU (PM8350_SID << 8 | 0x6b) 59*4882a593Smuzhiyun #define PM8350_ADC7_GPIO3_400K_PU (PM8350_SID << 8 | 0x6c) 60*4882a593Smuzhiyun #define PM8350_ADC7_GPIO4_400K_PU (PM8350_SID << 8 | 0x6d) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* 1/3 Divider */ 63*4882a593Smuzhiyun #define PM8350_ADC7_GPIO4_DIV3 (PM8350_SID << 8 | 0x8d) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define PM8350_ADC7_VPH_PWR (PM8350_SID << 8 | 0x8e) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */ 68