1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2017 Socionext Inc. 3*4882a593Smuzhiyun * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_GPIO_UNIPHIER_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_GPIO_UNIPHIER_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define UNIPHIER_GPIO_LINES_PER_BANK 8 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define UNIPHIER_GPIO_PORT(bank, line) \ 14*4882a593Smuzhiyun ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line)) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n)) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */ 19