1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * This header provides constants for binding nvidia,tegra194-gpio*. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 8*4882a593Smuzhiyun * provide names for this. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * The second cell contains standard flag values specified in gpio.h. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef _DT_BINDINGS_GPIO_TEGRA194_GPIO_H 14*4882a593Smuzhiyun #define _DT_BINDINGS_GPIO_TEGRA194_GPIO_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <dt-bindings/gpio/gpio.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* GPIOs implemented by main GPIO controller */ 19*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_A 0 20*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_B 1 21*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_C 2 22*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_D 3 23*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_E 4 24*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_F 5 25*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_G 6 26*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_H 7 27*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_I 8 28*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_J 9 29*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_K 10 30*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_L 11 31*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_M 12 32*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_N 13 33*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_O 14 34*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_P 15 35*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_Q 16 36*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_R 17 37*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_S 18 38*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_T 19 39*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_U 20 40*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_V 21 41*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_W 22 42*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_X 23 43*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_Y 24 44*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_Z 25 45*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_FF 26 46*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO_PORT_GG 27 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define TEGRA194_MAIN_GPIO(port, offset) \ 49*4882a593Smuzhiyun ((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* GPIOs implemented by AON GPIO controller */ 52*4882a593Smuzhiyun #define TEGRA194_AON_GPIO_PORT_AA 0 53*4882a593Smuzhiyun #define TEGRA194_AON_GPIO_PORT_BB 1 54*4882a593Smuzhiyun #define TEGRA194_AON_GPIO_PORT_CC 2 55*4882a593Smuzhiyun #define TEGRA194_AON_GPIO_PORT_DD 3 56*4882a593Smuzhiyun #define TEGRA194_AON_GPIO_PORT_EE 4 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define TEGRA194_AON_GPIO(port, offset) \ 59*4882a593Smuzhiyun ((TEGRA194_AON_GPIO_PORT_##port * 8) + offset) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif 62