1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants for binding nvidia,tegra186-gpio*. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 6*4882a593Smuzhiyun * provide names for this. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * The second cell contains standard flag values specified in gpio.h. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H 12*4882a593Smuzhiyun #define _DT_BINDINGS_GPIO_TEGRA_GPIO_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <dt-bindings/gpio/gpio.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* GPIOs implemented by main GPIO controller */ 17*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_A 0 18*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_B 1 19*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_C 2 20*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_D 3 21*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_E 4 22*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_F 5 23*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_G 6 24*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_H 7 25*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_I 8 26*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_J 9 27*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_K 10 28*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_L 11 29*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_M 12 30*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_N 13 31*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_O 14 32*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_P 15 33*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_Q 16 34*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_R 17 35*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_T 18 36*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_X 19 37*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_Y 20 38*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_BB 21 39*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO_PORT_CC 22 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define TEGRA186_MAIN_GPIO(port, offset) \ 42*4882a593Smuzhiyun ((TEGRA186_MAIN_GPIO_PORT_##port * 8) + offset) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* GPIOs implemented by AON GPIO controller */ 45*4882a593Smuzhiyun #define TEGRA186_AON_GPIO_PORT_S 0 46*4882a593Smuzhiyun #define TEGRA186_AON_GPIO_PORT_U 1 47*4882a593Smuzhiyun #define TEGRA186_AON_GPIO_PORT_V 2 48*4882a593Smuzhiyun #define TEGRA186_AON_GPIO_PORT_W 3 49*4882a593Smuzhiyun #define TEGRA186_AON_GPIO_PORT_Z 4 50*4882a593Smuzhiyun #define TEGRA186_AON_GPIO_PORT_AA 5 51*4882a593Smuzhiyun #define TEGRA186_AON_GPIO_PORT_EE 6 52*4882a593Smuzhiyun #define TEGRA186_AON_GPIO_PORT_FF 7 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define TEGRA186_AON_GPIO(port, offset) \ 55*4882a593Smuzhiyun ((TEGRA186_AON_GPIO_PORT_##port * 8) + offset) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #endif 58