1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants for binding nvidia,tegra*-gpio. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 6*4882a593Smuzhiyun * provide names for this. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * The second cell contains standard flag values specified in gpio.h. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H 12*4882a593Smuzhiyun #define _DT_BINDINGS_GPIO_TEGRA_GPIO_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <dt-bindings/gpio/gpio.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_A 0 17*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_B 1 18*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_C 2 19*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_D 3 20*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_E 4 21*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_F 5 22*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_G 6 23*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_H 7 24*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_I 8 25*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_J 9 26*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_K 10 27*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_L 11 28*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_M 12 29*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_N 13 30*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_O 14 31*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_P 15 32*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_Q 16 33*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_R 17 34*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_S 18 35*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_T 19 36*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_U 20 37*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_V 21 38*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_W 22 39*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_X 23 40*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_Y 24 41*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_Z 25 42*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_AA 26 43*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_BB 27 44*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_CC 28 45*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_DD 29 46*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_EE 30 47*4882a593Smuzhiyun #define TEGRA_GPIO_PORT_FF 31 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define TEGRA_GPIO(port, offset) \ 50*4882a593Smuzhiyun ((TEGRA_GPIO_PORT_##port * 8) + offset) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #endif 53