1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Houlong Wei <houlong.wei@mediatek.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DT_BINDINGS_GCE_MT8173_H 9*4882a593Smuzhiyun #define _DT_BINDINGS_GCE_MT8173_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* GCE HW thread priority */ 12*4882a593Smuzhiyun #define CMDQ_THR_PRIO_LOWEST 0 13*4882a593Smuzhiyun #define CMDQ_THR_PRIO_HIGHEST 1 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* GCE SUBSYS */ 16*4882a593Smuzhiyun #define SUBSYS_1400XXXX 1 17*4882a593Smuzhiyun #define SUBSYS_1401XXXX 2 18*4882a593Smuzhiyun #define SUBSYS_1402XXXX 3 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* GCE HW EVENT */ 21*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_OVL0_SOF 11 22*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_OVL1_SOF 12 23*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA0_SOF 13 24*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA1_SOF 14 25*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA2_SOF 15 26*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_WDMA0_SOF 16 27*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_WDMA1_SOF 17 28*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_OVL0_EOF 39 29*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_OVL1_EOF 40 30*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA0_EOF 41 31*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA1_EOF 42 32*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA2_EOF 43 33*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_WDMA0_EOF 44 34*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_WDMA1_EOF 45 35*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX0_STREAM_EOF 53 36*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX1_STREAM_EOF 54 37*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX2_STREAM_EOF 55 38*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX3_STREAM_EOF 56 39*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX4_STREAM_EOF 57 40*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 63 41*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 64 42*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 65 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #endif 45