1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Dennis-YC Hsieh <dennis-yc.hsieh@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_GCE_MT6779_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_GCE_MT6779_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define CMDQ_NO_TIMEOUT 0xffffffff 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* GCE HW thread priority */ 13*4882a593Smuzhiyun #define CMDQ_THR_PRIO_LOWEST 0 14*4882a593Smuzhiyun #define CMDQ_THR_PRIO_1 1 15*4882a593Smuzhiyun #define CMDQ_THR_PRIO_2 2 16*4882a593Smuzhiyun #define CMDQ_THR_PRIO_3 3 17*4882a593Smuzhiyun #define CMDQ_THR_PRIO_4 4 18*4882a593Smuzhiyun #define CMDQ_THR_PRIO_5 5 19*4882a593Smuzhiyun #define CMDQ_THR_PRIO_6 6 20*4882a593Smuzhiyun #define CMDQ_THR_PRIO_HIGHEST 7 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* GCE subsys table */ 23*4882a593Smuzhiyun #define SUBSYS_1300XXXX 0 24*4882a593Smuzhiyun #define SUBSYS_1400XXXX 1 25*4882a593Smuzhiyun #define SUBSYS_1401XXXX 2 26*4882a593Smuzhiyun #define SUBSYS_1402XXXX 3 27*4882a593Smuzhiyun #define SUBSYS_1502XXXX 4 28*4882a593Smuzhiyun #define SUBSYS_1880XXXX 5 29*4882a593Smuzhiyun #define SUBSYS_1881XXXX 6 30*4882a593Smuzhiyun #define SUBSYS_1882XXXX 7 31*4882a593Smuzhiyun #define SUBSYS_1883XXXX 8 32*4882a593Smuzhiyun #define SUBSYS_1884XXXX 9 33*4882a593Smuzhiyun #define SUBSYS_1000XXXX 10 34*4882a593Smuzhiyun #define SUBSYS_1001XXXX 11 35*4882a593Smuzhiyun #define SUBSYS_1002XXXX 12 36*4882a593Smuzhiyun #define SUBSYS_1003XXXX 13 37*4882a593Smuzhiyun #define SUBSYS_1004XXXX 14 38*4882a593Smuzhiyun #define SUBSYS_1005XXXX 15 39*4882a593Smuzhiyun #define SUBSYS_1020XXXX 16 40*4882a593Smuzhiyun #define SUBSYS_1028XXXX 17 41*4882a593Smuzhiyun #define SUBSYS_1700XXXX 18 42*4882a593Smuzhiyun #define SUBSYS_1701XXXX 19 43*4882a593Smuzhiyun #define SUBSYS_1702XXXX 20 44*4882a593Smuzhiyun #define SUBSYS_1703XXXX 21 45*4882a593Smuzhiyun #define SUBSYS_1800XXXX 22 46*4882a593Smuzhiyun #define SUBSYS_1801XXXX 23 47*4882a593Smuzhiyun #define SUBSYS_1802XXXX 24 48*4882a593Smuzhiyun #define SUBSYS_1804XXXX 25 49*4882a593Smuzhiyun #define SUBSYS_1805XXXX 26 50*4882a593Smuzhiyun #define SUBSYS_1808XXXX 27 51*4882a593Smuzhiyun #define SUBSYS_180aXXXX 28 52*4882a593Smuzhiyun #define SUBSYS_180bXXXX 29 53*4882a593Smuzhiyun #define CMDQ_SUBSYS_OFF 32 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* GCE hardware events */ 56*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA0_SOF 0 57*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA1_SOF 1 58*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_RDMA0_SOF 2 59*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_RDMA1_SOF 3 60*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_RSZ0_SOF 4 61*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_RSZ1_SOF 5 62*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_TDSHP_SOF 6 63*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_WROT0_SOF 7 64*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_WROT1_SOF 8 65*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_OVL0_SOF 9 66*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_2L_OVL0_SOF 10 67*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_2L_OVL1_SOF 11 68*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_WDMA0_SOF 12 69*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_COLOR0_SOF 13 70*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_CCORR0_SOF 14 71*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_AAL0_SOF 15 72*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_GAMMA0_SOF 16 73*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_DITHER0_SOF 17 74*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_PWM0_SOF 18 75*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_DSI0_SOF 19 76*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_DPI0_SOF 20 77*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_POSTMASK0_SOF 21 78*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RSZ0_SOF 22 79*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_AAL_SOF 23 80*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_CCORR_SOF 24 81*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_DBI0_SOF 25 82*4882a593Smuzhiyun #define CMDQ_EVENT_ISP_RELAY_SOF 26 83*4882a593Smuzhiyun #define CMDQ_EVENT_IPU_RELAY_SOF 27 84*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA0_EOF 28 85*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA1_EOF 29 86*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_RDMA0_EOF 30 87*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_RDMA1_EOF 31 88*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_RSZ0_EOF 32 89*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_RSZ1_EOF 33 90*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_TDSHP_EOF 34 91*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_WROT0_W_EOF 35 92*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_WROT1_W_EOF 36 93*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_OVL0_EOF 37 94*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_2L_OVL0_EOF 38 95*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_2L_OVL1_EOF 39 96*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_WDMA0_EOF 40 97*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_COLOR0_EOF 41 98*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_CCORR0_EOF 42 99*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_AAL0_EOF 43 100*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_GAMMA0_EOF 44 101*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_DITHER0_EOF 45 102*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_DSI0_EOF 46 103*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_DPI0_EOF 47 104*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RSZ0_EOF 49 105*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_AAL_FRAME_DONE 50 106*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_CCORR_FRAME_DONE 51 107*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 52 108*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX0_STREAM_EOF 130 109*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX1_STREAM_EOF 131 110*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX2_STREAM_EOF 132 111*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX3_STREAM_EOF 133 112*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX4_STREAM_EOF 134 113*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX5_STREAM_EOF 135 114*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX6_STREAM_EOF 136 115*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX7_STREAM_EOF 137 116*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX8_STREAM_EOF 138 117*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX9_STREAM_EOF 139 118*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX10_STREAM_EOF 140 119*4882a593Smuzhiyun #define CMDQ_EVENT_MUTEX11_STREAM_EOF 141 120*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 142 121*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 143 122*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 144 123*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_RDMA3_UNDERRUN 145 124*4882a593Smuzhiyun #define CMDQ_EVENT_DSI0_TE 146 125*4882a593Smuzhiyun #define CMDQ_EVENT_DSI0_IRQ_EVENT 147 126*4882a593Smuzhiyun #define CMDQ_EVENT_DSI0_DONE_EVENT 148 127*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE 150 128*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_WDMA0_RST_DONE 151 129*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_WROT0_RST_DONE 153 130*4882a593Smuzhiyun #define CMDQ_EVENT_MDP_RDMA0_RST_DONE 154 131*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_OVL0_RST_DONE 155 132*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE 156 133*4882a593Smuzhiyun #define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE 157 134*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD0_EOF 257 135*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD1_EOF 258 136*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD2_EOF 259 137*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD3_EOF 260 138*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD4_EOF 261 139*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD5_EOF 262 140*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD6_EOF 263 141*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD7_EOF 264 142*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD8_EOF 265 143*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD9_EOF 266 144*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD10_EOF 267 145*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD11_EOF 268 146*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD12_EOF 269 147*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD13_EOF 270 148*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD14_EOF 271 149*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD15_EOF 272 150*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD16_EOF 273 151*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD17_EOF 274 152*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_CQ_THREAD18_EOF 275 153*4882a593Smuzhiyun #define CMDQ_EVENT_DIP_DMA_ERR_EVENT 276 154*4882a593Smuzhiyun #define CMDQ_EVENT_AMD_FRAME_DONE 277 155*4882a593Smuzhiyun #define CMDQ_EVENT_MFB_DONE 278 156*4882a593Smuzhiyun #define CMDQ_EVENT_WPE_A_EOF 279 157*4882a593Smuzhiyun #define CMDQ_EVENT_VENC_EOF 289 158*4882a593Smuzhiyun #define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 290 159*4882a593Smuzhiyun #define CMDQ_EVENT_JPEG_ENC_EOF 291 160*4882a593Smuzhiyun #define CMDQ_EVENT_VENC_MB_DONE 292 161*4882a593Smuzhiyun #define CMDQ_EVENT_VENC_128BYTE_CNT_DONE 293 162*4882a593Smuzhiyun #define CMDQ_EVENT_ISP_FRAME_DONE_A 321 163*4882a593Smuzhiyun #define CMDQ_EVENT_ISP_FRAME_DONE_B 322 164*4882a593Smuzhiyun #define CMDQ_EVENT_ISP_FRAME_DONE_C 323 165*4882a593Smuzhiyun #define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE 324 166*4882a593Smuzhiyun #define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE 325 167*4882a593Smuzhiyun #define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE 326 168*4882a593Smuzhiyun #define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE 327 169*4882a593Smuzhiyun #define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE 328 170*4882a593Smuzhiyun #define CMDQ_EVENT_ISP_TSF_DONE 329 171*4882a593Smuzhiyun #define CMDQ_EVENT_SENINF_0_FIFO_FULL 330 172*4882a593Smuzhiyun #define CMDQ_EVENT_SENINF_1_FIFO_FULL 331 173*4882a593Smuzhiyun #define CMDQ_EVENT_SENINF_2_FIFO_FULL 332 174*4882a593Smuzhiyun #define CMDQ_EVENT_SENINF_3_FIFO_FULL 333 175*4882a593Smuzhiyun #define CMDQ_EVENT_SENINF_4_FIFO_FULL 334 176*4882a593Smuzhiyun #define CMDQ_EVENT_SENINF_5_FIFO_FULL 335 177*4882a593Smuzhiyun #define CMDQ_EVENT_SENINF_6_FIFO_FULL 336 178*4882a593Smuzhiyun #define CMDQ_EVENT_SENINF_7_FIFO_FULL 337 179*4882a593Smuzhiyun #define CMDQ_EVENT_TG_OVRUN_A_INT_DLY 338 180*4882a593Smuzhiyun #define CMDQ_EVENT_TG_OVRUN_B_INT_DLY 339 181*4882a593Smuzhiyun #define CMDQ_EVENT_TG_OVRUN_C_INT 340 182*4882a593Smuzhiyun #define CMDQ_EVENT_TG_GRABERR_A_INT_DLY 341 183*4882a593Smuzhiyun #define CMDQ_EVENT_TG_GRABERR_B_INT_DLY 342 184*4882a593Smuzhiyun #define CMDQ_EVENT_TG_GRABERR_C_INT 343 185*4882a593Smuzhiyun #define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY 344 186*4882a593Smuzhiyun #define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY 345 187*4882a593Smuzhiyun #define CMDQ_EVENT_CQ_VR_SNAP_C_INT 346 188*4882a593Smuzhiyun #define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY 347 189*4882a593Smuzhiyun #define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY 348 190*4882a593Smuzhiyun #define CMDQ_EVENT_DMA_R1_ERROR_C_INT 349 191*4882a593Smuzhiyun #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0 353 192*4882a593Smuzhiyun #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1 354 193*4882a593Smuzhiyun #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2 355 194*4882a593Smuzhiyun #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3 356 195*4882a593Smuzhiyun #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0 385 196*4882a593Smuzhiyun #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1 386 197*4882a593Smuzhiyun #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2 387 198*4882a593Smuzhiyun #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3 388 199*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_0 416 200*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_1 417 201*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_2 418 202*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_3 419 203*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_4 420 204*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_5 421 205*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_6 422 206*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_7 423 207*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_8 424 208*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_9 425 209*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_10 426 210*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_11 427 211*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_12 428 212*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_13 429 213*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_14 430 214*4882a593Smuzhiyun #define CMDQ_EVENT_VDEC_EVENT_15 431 215*4882a593Smuzhiyun #define CMDQ_EVENT_FDVT_DONE 449 216*4882a593Smuzhiyun #define CMDQ_EVENT_FE_DONE 450 217*4882a593Smuzhiyun #define CMDQ_EVENT_RSC_EOF 451 218*4882a593Smuzhiyun #define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 452 219*4882a593Smuzhiyun #define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 453 220*4882a593Smuzhiyun #define CMDQ_EVENT_DSI0_TE_INFRA 898 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun #endif 223