1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define DDR3_DS_34ohm (1 << 1) 11*4882a593Smuzhiyun #define DDR3_DS_40ohm (0x0) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define LP2_DS_34ohm (0x1) 14*4882a593Smuzhiyun #define LP2_DS_40ohm (0x2) 15*4882a593Smuzhiyun #define LP2_DS_48ohm (0x3) 16*4882a593Smuzhiyun #define LP2_DS_60ohm (0x4) 17*4882a593Smuzhiyun #define LP2_DS_68_6ohm (0x5)/* optional */ 18*4882a593Smuzhiyun #define LP2_DS_80ohm (0x6) 19*4882a593Smuzhiyun #define LP2_DS_120ohm (0x7)/* optional */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define LP3_DS_34ohm (0x1) 22*4882a593Smuzhiyun #define LP3_DS_40ohm (0x2) 23*4882a593Smuzhiyun #define LP3_DS_48ohm (0x3) 24*4882a593Smuzhiyun #define LP3_DS_60ohm (0x4) 25*4882a593Smuzhiyun #define LP3_DS_80ohm (0x6) 26*4882a593Smuzhiyun #define LP3_DS_34D_40U (0x9) 27*4882a593Smuzhiyun #define LP3_DS_40D_48U (0xa) 28*4882a593Smuzhiyun #define LP3_DS_34D_48U (0xb) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define DDR3_ODT_DIS (0) 31*4882a593Smuzhiyun #define DDR3_ODT_40ohm ((1 << 2) | (1 << 6)) 32*4882a593Smuzhiyun #define DDR3_ODT_60ohm (1 << 2) 33*4882a593Smuzhiyun #define DDR3_ODT_120ohm (1 << 6) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define LP3_ODT_DIS (0) 36*4882a593Smuzhiyun #define LP3_ODT_60ohm (1) 37*4882a593Smuzhiyun #define LP3_ODT_120ohm (2) 38*4882a593Smuzhiyun #define LP3_ODT_240ohm (3) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_DISABLE (0) 41*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_451ohm (1) 42*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_225ohm (2) 43*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_150ohm (3) 44*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_112ohm (4) 45*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_90ohm (5) 46*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_75ohm (6) 47*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_64ohm (7) 48*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_56ohm (16) 49*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_50ohm (17) 50*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_45ohm (18) 51*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_41ohm (19) 52*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_37ohm (20) 53*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_34ohm (21) 54*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_33ohm (22) 55*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_30ohm (23) 56*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_28ohm (24) 57*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_26ohm (25) 58*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_25ohm (26) 59*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_23ohm (27) 60*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_22ohm (28) 61*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_21ohm (29) 62*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_20ohm (30) 63*4882a593Smuzhiyun #define PHY_DDR3_RON_RTT_19ohm (31) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_DISABLE (0) 66*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_480ohm (1) 67*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_240ohm (2) 68*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_160ohm (3) 69*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_120ohm (4) 70*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_96ohm (5) 71*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_80ohm (6) 72*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_68ohm (7) 73*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_60ohm (16) 74*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_53ohm (17) 75*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_48ohm (18) 76*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_43ohm (19) 77*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_40ohm (20) 78*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_37ohm (21) 79*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_34ohm (22) 80*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_32ohm (23) 81*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_30ohm (24) 82*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_28ohm (25) 83*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_26ohm (26) 84*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_25ohm (27) 85*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_24ohm (28) 86*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_22ohm (29) 87*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_21ohm (30) 88*4882a593Smuzhiyun #define PHY_LP23_RON_RTT_20ohm (31) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H */ 91