xref: /OK3568_Linux_fs/kernel/include/dt-bindings/dram/rockchip,rk322x.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1 /*
2  * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
3  *
4  * SPDX-License-Identifier: GPL-2.0+
5  */
6 
7 #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H
8 #define _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H
9 
10 #define DDR3_DS_34ohm		(1 << 1)
11 #define DDR3_DS_40ohm		(0x0)
12 
13 #define LP2_DS_34ohm		(0x1)
14 #define LP2_DS_40ohm		(0x2)
15 #define LP2_DS_48ohm		(0x3)
16 #define LP2_DS_60ohm		(0x4)
17 #define LP2_DS_68_6ohm		(0x5)/* optional */
18 #define LP2_DS_80ohm		(0x6)
19 #define LP2_DS_120ohm		(0x7)/* optional */
20 
21 #define LP3_DS_34ohm		(0x1)
22 #define LP3_DS_40ohm		(0x2)
23 #define LP3_DS_48ohm		(0x3)
24 #define LP3_DS_60ohm		(0x4)
25 #define LP3_DS_80ohm		(0x6)
26 #define LP3_DS_34D_40U		(0x9)
27 #define LP3_DS_40D_48U		(0xa)
28 #define LP3_DS_34D_48U		(0xb)
29 
30 #define DDR3_ODT_DIS		(0)
31 #define DDR3_ODT_40ohm		((1 << 2) | (1 << 6))
32 #define DDR3_ODT_60ohm		(1 << 2)
33 #define DDR3_ODT_120ohm		(1 << 6)
34 
35 #define LP3_ODT_DIS		(0)
36 #define LP3_ODT_60ohm		(1)
37 #define LP3_ODT_120ohm		(2)
38 #define LP3_ODT_240ohm		(3)
39 
40 #define PHY_DDR3_RON_RTT_DISABLE	(0)
41 #define PHY_DDR3_RON_RTT_451ohm		(1)
42 #define PHY_DDR3_RON_RTT_225ohm		(2)
43 #define PHY_DDR3_RON_RTT_150ohm		(3)
44 #define PHY_DDR3_RON_RTT_112ohm		(4)
45 #define PHY_DDR3_RON_RTT_90ohm		(5)
46 #define PHY_DDR3_RON_RTT_75ohm		(6)
47 #define PHY_DDR3_RON_RTT_64ohm		(7)
48 #define PHY_DDR3_RON_RTT_56ohm		(16)
49 #define PHY_DDR3_RON_RTT_50ohm		(17)
50 #define PHY_DDR3_RON_RTT_45ohm		(18)
51 #define PHY_DDR3_RON_RTT_41ohm		(19)
52 #define PHY_DDR3_RON_RTT_37ohm		(20)
53 #define PHY_DDR3_RON_RTT_34ohm		(21)
54 #define PHY_DDR3_RON_RTT_33ohm		(22)
55 #define PHY_DDR3_RON_RTT_30ohm		(23)
56 #define PHY_DDR3_RON_RTT_28ohm		(24)
57 #define PHY_DDR3_RON_RTT_26ohm		(25)
58 #define PHY_DDR3_RON_RTT_25ohm		(26)
59 #define PHY_DDR3_RON_RTT_23ohm		(27)
60 #define PHY_DDR3_RON_RTT_22ohm		(28)
61 #define PHY_DDR3_RON_RTT_21ohm		(29)
62 #define PHY_DDR3_RON_RTT_20ohm		(30)
63 #define PHY_DDR3_RON_RTT_19ohm		(31)
64 
65 #define PHY_LP23_RON_RTT_DISABLE	(0)
66 #define PHY_LP23_RON_RTT_480ohm		(1)
67 #define PHY_LP23_RON_RTT_240ohm		(2)
68 #define PHY_LP23_RON_RTT_160ohm		(3)
69 #define PHY_LP23_RON_RTT_120ohm		(4)
70 #define PHY_LP23_RON_RTT_96ohm		(5)
71 #define PHY_LP23_RON_RTT_80ohm		(6)
72 #define PHY_LP23_RON_RTT_68ohm		(7)
73 #define PHY_LP23_RON_RTT_60ohm		(16)
74 #define PHY_LP23_RON_RTT_53ohm		(17)
75 #define PHY_LP23_RON_RTT_48ohm		(18)
76 #define PHY_LP23_RON_RTT_43ohm		(19)
77 #define PHY_LP23_RON_RTT_40ohm		(20)
78 #define PHY_LP23_RON_RTT_37ohm		(21)
79 #define PHY_LP23_RON_RTT_34ohm		(22)
80 #define PHY_LP23_RON_RTT_32ohm		(23)
81 #define PHY_LP23_RON_RTT_30ohm		(24)
82 #define PHY_LP23_RON_RTT_28ohm		(25)
83 #define PHY_LP23_RON_RTT_26ohm		(26)
84 #define PHY_LP23_RON_RTT_25ohm		(27)
85 #define PHY_LP23_RON_RTT_24ohm		(28)
86 #define PHY_LP23_RON_RTT_22ohm		(29)
87 #define PHY_LP23_RON_RTT_21ohm		(30)
88 #define PHY_LP23_RON_RTT_20ohm		(31)
89 
90 #endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H */
91