1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides macros for X1830 DMA bindings. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DT_BINDINGS_DMA_X1830_DMA_H__ 9*4882a593Smuzhiyun #define __DT_BINDINGS_DMA_X1830_DMA_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Request type numbers for the X1830 DMA controller (written to the DRTn 13*4882a593Smuzhiyun * register for the channel). 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define X1830_DMA_I2S0_TX 0x6 16*4882a593Smuzhiyun #define X1830_DMA_I2S0_RX 0x7 17*4882a593Smuzhiyun #define X1830_DMA_AUTO 0x8 18*4882a593Smuzhiyun #define X1830_DMA_SADC_RX 0x9 19*4882a593Smuzhiyun #define X1830_DMA_UART1_TX 0x12 20*4882a593Smuzhiyun #define X1830_DMA_UART1_RX 0x13 21*4882a593Smuzhiyun #define X1830_DMA_UART0_TX 0x14 22*4882a593Smuzhiyun #define X1830_DMA_UART0_RX 0x15 23*4882a593Smuzhiyun #define X1830_DMA_SSI0_TX 0x16 24*4882a593Smuzhiyun #define X1830_DMA_SSI0_RX 0x17 25*4882a593Smuzhiyun #define X1830_DMA_SSI1_TX 0x18 26*4882a593Smuzhiyun #define X1830_DMA_SSI1_RX 0x19 27*4882a593Smuzhiyun #define X1830_DMA_MSC0_TX 0x1a 28*4882a593Smuzhiyun #define X1830_DMA_MSC0_RX 0x1b 29*4882a593Smuzhiyun #define X1830_DMA_MSC1_TX 0x1c 30*4882a593Smuzhiyun #define X1830_DMA_MSC1_RX 0x1d 31*4882a593Smuzhiyun #define X1830_DMA_DMIC_RX 0x21 32*4882a593Smuzhiyun #define X1830_DMA_SMB0_TX 0x24 33*4882a593Smuzhiyun #define X1830_DMA_SMB0_RX 0x25 34*4882a593Smuzhiyun #define X1830_DMA_SMB1_TX 0x26 35*4882a593Smuzhiyun #define X1830_DMA_SMB1_RX 0x27 36*4882a593Smuzhiyun #define X1830_DMA_DES_TX 0x2e 37*4882a593Smuzhiyun #define X1830_DMA_DES_RX 0x2f 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #endif /* __DT_BINDINGS_DMA_X1830_DMA_H__ */ 40