1*4882a593Smuzhiyun #ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__ 2*4882a593Smuzhiyun #define __DT_BINDINGS_DMA_JZ4780_DMA_H__ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * Request type numbers for the JZ4780 DMA controller (written to the DRTn 6*4882a593Smuzhiyun * register for the channel). 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #define JZ4780_DMA_I2S1_TX 0x4 9*4882a593Smuzhiyun #define JZ4780_DMA_I2S1_RX 0x5 10*4882a593Smuzhiyun #define JZ4780_DMA_I2S0_TX 0x6 11*4882a593Smuzhiyun #define JZ4780_DMA_I2S0_RX 0x7 12*4882a593Smuzhiyun #define JZ4780_DMA_AUTO 0x8 13*4882a593Smuzhiyun #define JZ4780_DMA_SADC_RX 0x9 14*4882a593Smuzhiyun #define JZ4780_DMA_UART4_TX 0xc 15*4882a593Smuzhiyun #define JZ4780_DMA_UART4_RX 0xd 16*4882a593Smuzhiyun #define JZ4780_DMA_UART3_TX 0xe 17*4882a593Smuzhiyun #define JZ4780_DMA_UART3_RX 0xf 18*4882a593Smuzhiyun #define JZ4780_DMA_UART2_TX 0x10 19*4882a593Smuzhiyun #define JZ4780_DMA_UART2_RX 0x11 20*4882a593Smuzhiyun #define JZ4780_DMA_UART1_TX 0x12 21*4882a593Smuzhiyun #define JZ4780_DMA_UART1_RX 0x13 22*4882a593Smuzhiyun #define JZ4780_DMA_UART0_TX 0x14 23*4882a593Smuzhiyun #define JZ4780_DMA_UART0_RX 0x15 24*4882a593Smuzhiyun #define JZ4780_DMA_SSI0_TX 0x16 25*4882a593Smuzhiyun #define JZ4780_DMA_SSI0_RX 0x17 26*4882a593Smuzhiyun #define JZ4780_DMA_SSI1_TX 0x18 27*4882a593Smuzhiyun #define JZ4780_DMA_SSI1_RX 0x19 28*4882a593Smuzhiyun #define JZ4780_DMA_MSC0_TX 0x1a 29*4882a593Smuzhiyun #define JZ4780_DMA_MSC0_RX 0x1b 30*4882a593Smuzhiyun #define JZ4780_DMA_MSC1_TX 0x1c 31*4882a593Smuzhiyun #define JZ4780_DMA_MSC1_RX 0x1d 32*4882a593Smuzhiyun #define JZ4780_DMA_MSC2_TX 0x1e 33*4882a593Smuzhiyun #define JZ4780_DMA_MSC2_RX 0x1f 34*4882a593Smuzhiyun #define JZ4780_DMA_PCM0_TX 0x20 35*4882a593Smuzhiyun #define JZ4780_DMA_PCM0_RX 0x21 36*4882a593Smuzhiyun #define JZ4780_DMA_SMB0_TX 0x24 37*4882a593Smuzhiyun #define JZ4780_DMA_SMB0_RX 0x25 38*4882a593Smuzhiyun #define JZ4780_DMA_SMB1_TX 0x26 39*4882a593Smuzhiyun #define JZ4780_DMA_SMB1_RX 0x27 40*4882a593Smuzhiyun #define JZ4780_DMA_SMB2_TX 0x28 41*4882a593Smuzhiyun #define JZ4780_DMA_SMB2_RX 0x29 42*4882a593Smuzhiyun #define JZ4780_DMA_SMB3_TX 0x2a 43*4882a593Smuzhiyun #define JZ4780_DMA_SMB3_RX 0x2b 44*4882a593Smuzhiyun #define JZ4780_DMA_SMB4_TX 0x2c 45*4882a593Smuzhiyun #define JZ4780_DMA_SMB4_RX 0x2d 46*4882a593Smuzhiyun #define JZ4780_DMA_DES_TX 0x2e 47*4882a593Smuzhiyun #define JZ4780_DMA_DES_RX 0x2f 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */ 50