1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun drivers/video/rockchip/transmitter/mipi_dsi.h 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef MIPI_DSI_H_ 6*4882a593Smuzhiyun #define MIPI_DSI_H_ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifdef CONFIG_MIPI_DSI_FT 9*4882a593Smuzhiyun #include "..\..\common\config.h" 10*4882a593Smuzhiyun #endif 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun //DSI DATA TYPE 13*4882a593Smuzhiyun #define DTYPE_DCS_SWRITE_0P 0x05 14*4882a593Smuzhiyun #define DTYPE_DCS_SWRITE_1P 0x15 15*4882a593Smuzhiyun #define DTYPE_DCS_LWRITE 0x39 16*4882a593Smuzhiyun #define DTYPE_GEN_LWRITE 0x29 17*4882a593Smuzhiyun #define DTYPE_GEN_SWRITE_2P 0x23 18*4882a593Smuzhiyun #define DTYPE_GEN_SWRITE_1P 0x13 19*4882a593Smuzhiyun #define DTYPE_GEN_SWRITE_0P 0x03 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun //command transmit mode 22*4882a593Smuzhiyun #define HSDT 0x00 23*4882a593Smuzhiyun #define LPDT 0x01 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun //DSI DATA TYPE FLAG 26*4882a593Smuzhiyun #define DATA_TYPE_DCS 0x00 27*4882a593Smuzhiyun #define DATA_TYPE_GEN 0x01 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun //Video Mode 30*4882a593Smuzhiyun #define VM_NBMWSP 0x00 //Non burst mode with sync pulses 31*4882a593Smuzhiyun #define VM_NBMWSE 0x01 //Non burst mode with sync events 32*4882a593Smuzhiyun #define VM_BM 0x02 //Burst mode 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun //Video Pixel Format 35*4882a593Smuzhiyun #define VPF_16BPP 0x00 36*4882a593Smuzhiyun #define VPF_18BPP 0x01 //packed 37*4882a593Smuzhiyun #define VPF_18BPPL 0x02 //loosely packed 38*4882a593Smuzhiyun #define VPF_24BPP 0x03 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun //Display Command Set 41*4882a593Smuzhiyun #define dcs_enter_idle_mode 0x39 42*4882a593Smuzhiyun #define dcs_enter_invert_mode 0x21 43*4882a593Smuzhiyun #define dcs_enter_normal_mode 0x13 44*4882a593Smuzhiyun #define dcs_enter_partial_mode 0x12 45*4882a593Smuzhiyun #define dcs_enter_sleep_mode 0x10 46*4882a593Smuzhiyun #define dcs_exit_idle_mode 0x38 47*4882a593Smuzhiyun #define dcs_exit_invert_mode 0x20 48*4882a593Smuzhiyun #define dcs_exit_sleep_mode 0x11 49*4882a593Smuzhiyun #define dcs_get_address_mode 0x0b 50*4882a593Smuzhiyun #define dcs_get_blue_channel 0x08 51*4882a593Smuzhiyun #define dcs_get_diagnostic_result 0x0f 52*4882a593Smuzhiyun #define dcs_get_display_mode 0x0d 53*4882a593Smuzhiyun #define dcs_get_green_channel 0x07 54*4882a593Smuzhiyun #define dcs_get_pixel_format 0x0c 55*4882a593Smuzhiyun #define dcs_get_power_mode 0x0a 56*4882a593Smuzhiyun #define dcs_get_red_channel 0x06 57*4882a593Smuzhiyun #define dcs_get_scanline 0x45 58*4882a593Smuzhiyun #define dcs_get_signal_mode 0x0e 59*4882a593Smuzhiyun #define dcs_nop 0x00 60*4882a593Smuzhiyun #define dcs_read_DDB_continue 0xa8 61*4882a593Smuzhiyun #define dcs_read_DDB_start 0xa1 62*4882a593Smuzhiyun #define dcs_read_memory_continue 0x3e 63*4882a593Smuzhiyun #define dcs_read_memory_start 0x2e 64*4882a593Smuzhiyun #define dcs_set_address_mode 0x36 65*4882a593Smuzhiyun #define dcs_set_column_address 0x2a 66*4882a593Smuzhiyun #define dcs_set_display_off 0x28 67*4882a593Smuzhiyun #define dcs_set_display_on 0x29 68*4882a593Smuzhiyun #define dcs_set_gamma_curve 0x26 69*4882a593Smuzhiyun #define dcs_set_page_address 0x2b 70*4882a593Smuzhiyun #define dcs_set_partial_area 0x30 71*4882a593Smuzhiyun #define dcs_set_pixel_format 0x3a 72*4882a593Smuzhiyun #define dcs_set_scroll_area 0x33 73*4882a593Smuzhiyun #define dcs_set_scroll_start 0x37 74*4882a593Smuzhiyun #define dcs_set_tear_off 0x34 75*4882a593Smuzhiyun #define dcs_set_tear_on 0x35 76*4882a593Smuzhiyun #define dcs_set_tear_scanline 0x44 77*4882a593Smuzhiyun #define dcs_soft_reset 0x01 78*4882a593Smuzhiyun #define dcs_write_LUT 0x2d 79*4882a593Smuzhiyun #define dcs_write_memory_continue 0x3c 80*4882a593Smuzhiyun #define dcs_write_memory_start 0x2c 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #ifndef MHz 83*4882a593Smuzhiyun #define MHz 1000000 84*4882a593Smuzhiyun #endif 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #if 0 88*4882a593Smuzhiyun typedef signed char s8; 89*4882a593Smuzhiyun typedef unsigned char u8; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun typedef signed short s16; 92*4882a593Smuzhiyun typedef unsigned short u16; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun typedef signed int s32; 95*4882a593Smuzhiyun typedef unsigned int u32; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun typedef signed long s64; 98*4882a593Smuzhiyun typedef unsigned long u64; 99*4882a593Smuzhiyun #endif 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun //iomux 103*4882a593Smuzhiyun #define OLD_RK_IOMUX 0 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #endif /* end of MIPI_DSI_H_ */ 107