1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * MIPI DSI Bus 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) Fuzhou Rockchip Electronics Co.Ltd 5*4882a593Smuzhiyun * Authors: 6*4882a593Smuzhiyun * Mark Yao <yzq@rock-chips.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * based on include/drm/drm_mipi_dsi.h 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 11*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 12*4882a593Smuzhiyun * published by the Free Software Foundation. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef _DRM_MIPI_DSI_H__ 16*4882a593Smuzhiyun #define _DRM_MIPI_DSI_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* DSI mode flags */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* video mode */ 21*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO (1 << 0) 22*4882a593Smuzhiyun /* video burst mode */ 23*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_BURST (1 << 1) 24*4882a593Smuzhiyun /* video pulse mode */ 25*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_SYNC_PULSE (1 << 2) 26*4882a593Smuzhiyun /* enable auto vertical count mode */ 27*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_AUTO_VERT (1 << 3) 28*4882a593Smuzhiyun /* enable hsync-end packets in vsync-pulse and v-porch area */ 29*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_HSE (1 << 4) 30*4882a593Smuzhiyun /* disable hfront-porch area */ 31*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_HFP (1 << 5) 32*4882a593Smuzhiyun /* disable hback-porch area */ 33*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_HBP (1 << 6) 34*4882a593Smuzhiyun /* disable hsync-active area */ 35*4882a593Smuzhiyun #define MIPI_DSI_MODE_VIDEO_HSA (1 << 7) 36*4882a593Smuzhiyun /* flush display FIFO on vsync pulse */ 37*4882a593Smuzhiyun #define MIPI_DSI_MODE_VSYNC_FLUSH (1 << 8) 38*4882a593Smuzhiyun /* disable EoT packets in HS mode */ 39*4882a593Smuzhiyun #define MIPI_DSI_MODE_EOT_PACKET (1 << 9) 40*4882a593Smuzhiyun /* device supports non-continuous clock behavior (DSI spec 5.6.1) */ 41*4882a593Smuzhiyun #define MIPI_DSI_CLOCK_NON_CONTINUOUS (1 << 10) 42*4882a593Smuzhiyun /* transmit data in low power */ 43*4882a593Smuzhiyun #define MIPI_DSI_MODE_LPM (1 << 11) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define MIPI_DSI_FMT_RGB888 0 46*4882a593Smuzhiyun #define MIPI_DSI_FMT_RGB666 1 47*4882a593Smuzhiyun #define MIPI_DSI_FMT_RGB666_PACKED 2 48*4882a593Smuzhiyun #define MIPI_DSI_FMT_RGB565 3 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define MIPI_CSI_FMT_RAW8 0x10 51*4882a593Smuzhiyun #define MIPI_CSI_FMT_RAW10 0x11 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #endif /* __DRM_MIPI_DSI__ */ 54