1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2014 Linaro Ltd. 4*4882a593Smuzhiyun * Copyright (C) 2014 ZTE Corporation. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_ZX296702_H 8*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_ZX296702_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define ZX296702_OSC 0 11*4882a593Smuzhiyun #define ZX296702_PLL_A9 1 12*4882a593Smuzhiyun #define ZX296702_PLL_A9_350M 2 13*4882a593Smuzhiyun #define ZX296702_PLL_MAC_1000M 3 14*4882a593Smuzhiyun #define ZX296702_PLL_MAC_333M 4 15*4882a593Smuzhiyun #define ZX296702_PLL_MM0_1188M 5 16*4882a593Smuzhiyun #define ZX296702_PLL_MM0_396M 6 17*4882a593Smuzhiyun #define ZX296702_PLL_MM0_198M 7 18*4882a593Smuzhiyun #define ZX296702_PLL_MM1_108M 8 19*4882a593Smuzhiyun #define ZX296702_PLL_MM1_72M 9 20*4882a593Smuzhiyun #define ZX296702_PLL_MM1_54M 10 21*4882a593Smuzhiyun #define ZX296702_PLL_LSP_104M 11 22*4882a593Smuzhiyun #define ZX296702_PLL_LSP_26M 12 23*4882a593Smuzhiyun #define ZX296702_PLL_AUDIO_294M912 13 24*4882a593Smuzhiyun #define ZX296702_PLL_DDR_266M 14 25*4882a593Smuzhiyun #define ZX296702_CLK_148M5 15 26*4882a593Smuzhiyun #define ZX296702_MATRIX_ACLK 16 27*4882a593Smuzhiyun #define ZX296702_MAIN_HCLK 17 28*4882a593Smuzhiyun #define ZX296702_MAIN_PCLK 18 29*4882a593Smuzhiyun #define ZX296702_CLK_500 19 30*4882a593Smuzhiyun #define ZX296702_CLK_250 20 31*4882a593Smuzhiyun #define ZX296702_CLK_125 21 32*4882a593Smuzhiyun #define ZX296702_CLK_74M25 22 33*4882a593Smuzhiyun #define ZX296702_A9_WCLK 23 34*4882a593Smuzhiyun #define ZX296702_A9_AS1_ACLK_MUX 24 35*4882a593Smuzhiyun #define ZX296702_A9_TRACE_CLKIN_MUX 25 36*4882a593Smuzhiyun #define ZX296702_A9_AS1_ACLK_DIV 26 37*4882a593Smuzhiyun #define ZX296702_CLK_2 27 38*4882a593Smuzhiyun #define ZX296702_CLK_27 28 39*4882a593Smuzhiyun #define ZX296702_DECPPU_ACLK_MUX 29 40*4882a593Smuzhiyun #define ZX296702_PPU_ACLK_MUX 30 41*4882a593Smuzhiyun #define ZX296702_MALI400_ACLK_MUX 31 42*4882a593Smuzhiyun #define ZX296702_VOU_ACLK_MUX 32 43*4882a593Smuzhiyun #define ZX296702_VOU_MAIN_WCLK_MUX 33 44*4882a593Smuzhiyun #define ZX296702_VOU_AUX_WCLK_MUX 34 45*4882a593Smuzhiyun #define ZX296702_VOU_SCALER_WCLK_MUX 35 46*4882a593Smuzhiyun #define ZX296702_R2D_ACLK_MUX 36 47*4882a593Smuzhiyun #define ZX296702_R2D_WCLK_MUX 37 48*4882a593Smuzhiyun #define ZX296702_CLK_50 38 49*4882a593Smuzhiyun #define ZX296702_CLK_25 39 50*4882a593Smuzhiyun #define ZX296702_CLK_12 40 51*4882a593Smuzhiyun #define ZX296702_CLK_16M384 41 52*4882a593Smuzhiyun #define ZX296702_CLK_32K768 42 53*4882a593Smuzhiyun #define ZX296702_SEC_WCLK_DIV 43 54*4882a593Smuzhiyun #define ZX296702_DDR_WCLK_MUX 44 55*4882a593Smuzhiyun #define ZX296702_NAND_WCLK_MUX 45 56*4882a593Smuzhiyun #define ZX296702_LSP_26_WCLK_MUX 46 57*4882a593Smuzhiyun #define ZX296702_A9_AS0_ACLK 47 58*4882a593Smuzhiyun #define ZX296702_A9_AS1_ACLK 48 59*4882a593Smuzhiyun #define ZX296702_A9_TRACE_CLKIN 49 60*4882a593Smuzhiyun #define ZX296702_DECPPU_AXI_M_ACLK 50 61*4882a593Smuzhiyun #define ZX296702_DECPPU_AHB_S_HCLK 51 62*4882a593Smuzhiyun #define ZX296702_PPU_AXI_M_ACLK 52 63*4882a593Smuzhiyun #define ZX296702_PPU_AHB_S_HCLK 53 64*4882a593Smuzhiyun #define ZX296702_VOU_AXI_M_ACLK 54 65*4882a593Smuzhiyun #define ZX296702_VOU_APB_PCLK 55 66*4882a593Smuzhiyun #define ZX296702_VOU_MAIN_CHANNEL_WCLK 56 67*4882a593Smuzhiyun #define ZX296702_VOU_AUX_CHANNEL_WCLK 57 68*4882a593Smuzhiyun #define ZX296702_VOU_HDMI_OSCLK_CEC 58 69*4882a593Smuzhiyun #define ZX296702_VOU_SCALER_WCLK 59 70*4882a593Smuzhiyun #define ZX296702_MALI400_AXI_M_ACLK 60 71*4882a593Smuzhiyun #define ZX296702_MALI400_APB_PCLK 61 72*4882a593Smuzhiyun #define ZX296702_R2D_WCLK 62 73*4882a593Smuzhiyun #define ZX296702_R2D_AXI_M_ACLK 63 74*4882a593Smuzhiyun #define ZX296702_R2D_AHB_HCLK 64 75*4882a593Smuzhiyun #define ZX296702_DDR3_AXI_S0_ACLK 65 76*4882a593Smuzhiyun #define ZX296702_DDR3_APB_PCLK 66 77*4882a593Smuzhiyun #define ZX296702_DDR3_WCLK 67 78*4882a593Smuzhiyun #define ZX296702_USB20_0_AHB_HCLK 68 79*4882a593Smuzhiyun #define ZX296702_USB20_0_EXTREFCLK 69 80*4882a593Smuzhiyun #define ZX296702_USB20_1_AHB_HCLK 70 81*4882a593Smuzhiyun #define ZX296702_USB20_1_EXTREFCLK 71 82*4882a593Smuzhiyun #define ZX296702_USB20_2_AHB_HCLK 72 83*4882a593Smuzhiyun #define ZX296702_USB20_2_EXTREFCLK 73 84*4882a593Smuzhiyun #define ZX296702_GMAC_AXI_M_ACLK 74 85*4882a593Smuzhiyun #define ZX296702_GMAC_APB_PCLK 75 86*4882a593Smuzhiyun #define ZX296702_GMAC_125_CLKIN 76 87*4882a593Smuzhiyun #define ZX296702_GMAC_RMII_CLKIN 77 88*4882a593Smuzhiyun #define ZX296702_GMAC_25M_CLK 78 89*4882a593Smuzhiyun #define ZX296702_NANDFLASH_AHB_HCLK 79 90*4882a593Smuzhiyun #define ZX296702_NANDFLASH_WCLK 80 91*4882a593Smuzhiyun #define ZX296702_LSP0_APB_PCLK 81 92*4882a593Smuzhiyun #define ZX296702_LSP0_AHB_HCLK 82 93*4882a593Smuzhiyun #define ZX296702_LSP0_26M_WCLK 83 94*4882a593Smuzhiyun #define ZX296702_LSP0_104M_WCLK 84 95*4882a593Smuzhiyun #define ZX296702_LSP0_16M384_WCLK 85 96*4882a593Smuzhiyun #define ZX296702_LSP1_APB_PCLK 86 97*4882a593Smuzhiyun #define ZX296702_LSP1_26M_WCLK 87 98*4882a593Smuzhiyun #define ZX296702_LSP1_104M_WCLK 88 99*4882a593Smuzhiyun #define ZX296702_LSP1_32K_CLK 89 100*4882a593Smuzhiyun #define ZX296702_AON_HCLK 90 101*4882a593Smuzhiyun #define ZX296702_SYS_CTRL_PCLK 91 102*4882a593Smuzhiyun #define ZX296702_DMA_PCLK 92 103*4882a593Smuzhiyun #define ZX296702_DMA_ACLK 93 104*4882a593Smuzhiyun #define ZX296702_SEC_HCLK 94 105*4882a593Smuzhiyun #define ZX296702_AES_WCLK 95 106*4882a593Smuzhiyun #define ZX296702_DES_WCLK 96 107*4882a593Smuzhiyun #define ZX296702_IRAM_ACLK 97 108*4882a593Smuzhiyun #define ZX296702_IROM_ACLK 98 109*4882a593Smuzhiyun #define ZX296702_BOOT_CTRL_HCLK 99 110*4882a593Smuzhiyun #define ZX296702_EFUSE_CLK_30 100 111*4882a593Smuzhiyun #define ZX296702_VOU_MAIN_CHANNEL_DIV 101 112*4882a593Smuzhiyun #define ZX296702_VOU_AUX_CHANNEL_DIV 102 113*4882a593Smuzhiyun #define ZX296702_VOU_TV_ENC_HD_DIV 103 114*4882a593Smuzhiyun #define ZX296702_VOU_TV_ENC_SD_DIV 104 115*4882a593Smuzhiyun #define ZX296702_VL0_MUX 105 116*4882a593Smuzhiyun #define ZX296702_VL1_MUX 106 117*4882a593Smuzhiyun #define ZX296702_VL2_MUX 107 118*4882a593Smuzhiyun #define ZX296702_GL0_MUX 108 119*4882a593Smuzhiyun #define ZX296702_GL1_MUX 109 120*4882a593Smuzhiyun #define ZX296702_GL2_MUX 110 121*4882a593Smuzhiyun #define ZX296702_WB_MUX 111 122*4882a593Smuzhiyun #define ZX296702_HDMI_MUX 112 123*4882a593Smuzhiyun #define ZX296702_VOU_TV_ENC_HD_MUX 113 124*4882a593Smuzhiyun #define ZX296702_VOU_TV_ENC_SD_MUX 114 125*4882a593Smuzhiyun #define ZX296702_VL0_CLK 115 126*4882a593Smuzhiyun #define ZX296702_VL1_CLK 116 127*4882a593Smuzhiyun #define ZX296702_VL2_CLK 117 128*4882a593Smuzhiyun #define ZX296702_GL0_CLK 118 129*4882a593Smuzhiyun #define ZX296702_GL1_CLK 119 130*4882a593Smuzhiyun #define ZX296702_GL2_CLK 120 131*4882a593Smuzhiyun #define ZX296702_WB_CLK 121 132*4882a593Smuzhiyun #define ZX296702_CL_CLK 122 133*4882a593Smuzhiyun #define ZX296702_MAIN_MIX_CLK 123 134*4882a593Smuzhiyun #define ZX296702_AUX_MIX_CLK 124 135*4882a593Smuzhiyun #define ZX296702_HDMI_CLK 125 136*4882a593Smuzhiyun #define ZX296702_VOU_TV_ENC_HD_DAC_CLK 126 137*4882a593Smuzhiyun #define ZX296702_VOU_TV_ENC_SD_DAC_CLK 127 138*4882a593Smuzhiyun #define ZX296702_A9_PERIPHCLK 128 139*4882a593Smuzhiyun #define ZX296702_TOPCLK_END 129 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define ZX296702_SDMMC1_WCLK_MUX 0 142*4882a593Smuzhiyun #define ZX296702_SDMMC1_WCLK_DIV 1 143*4882a593Smuzhiyun #define ZX296702_SDMMC1_WCLK 2 144*4882a593Smuzhiyun #define ZX296702_SDMMC1_PCLK 3 145*4882a593Smuzhiyun #define ZX296702_SPDIF0_WCLK_MUX 4 146*4882a593Smuzhiyun #define ZX296702_SPDIF0_WCLK 5 147*4882a593Smuzhiyun #define ZX296702_SPDIF0_PCLK 6 148*4882a593Smuzhiyun #define ZX296702_SPDIF0_DIV 7 149*4882a593Smuzhiyun #define ZX296702_I2S0_WCLK_MUX 8 150*4882a593Smuzhiyun #define ZX296702_I2S0_WCLK 9 151*4882a593Smuzhiyun #define ZX296702_I2S0_PCLK 10 152*4882a593Smuzhiyun #define ZX296702_I2S0_DIV 11 153*4882a593Smuzhiyun #define ZX296702_I2S1_WCLK_MUX 12 154*4882a593Smuzhiyun #define ZX296702_I2S1_WCLK 13 155*4882a593Smuzhiyun #define ZX296702_I2S1_PCLK 14 156*4882a593Smuzhiyun #define ZX296702_I2S1_DIV 15 157*4882a593Smuzhiyun #define ZX296702_I2S2_WCLK_MUX 16 158*4882a593Smuzhiyun #define ZX296702_I2S2_WCLK 17 159*4882a593Smuzhiyun #define ZX296702_I2S2_PCLK 18 160*4882a593Smuzhiyun #define ZX296702_I2S2_DIV 19 161*4882a593Smuzhiyun #define ZX296702_GPIO_CLK 20 162*4882a593Smuzhiyun #define ZX296702_LSP0CLK_END 21 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #define ZX296702_UART0_WCLK_MUX 0 165*4882a593Smuzhiyun #define ZX296702_UART0_WCLK 1 166*4882a593Smuzhiyun #define ZX296702_UART0_PCLK 2 167*4882a593Smuzhiyun #define ZX296702_UART1_WCLK_MUX 3 168*4882a593Smuzhiyun #define ZX296702_UART1_WCLK 4 169*4882a593Smuzhiyun #define ZX296702_UART1_PCLK 5 170*4882a593Smuzhiyun #define ZX296702_SDMMC0_WCLK_MUX 6 171*4882a593Smuzhiyun #define ZX296702_SDMMC0_WCLK_DIV 7 172*4882a593Smuzhiyun #define ZX296702_SDMMC0_WCLK 8 173*4882a593Smuzhiyun #define ZX296702_SDMMC0_PCLK 9 174*4882a593Smuzhiyun #define ZX296702_SPDIF1_WCLK_MUX 10 175*4882a593Smuzhiyun #define ZX296702_SPDIF1_WCLK 11 176*4882a593Smuzhiyun #define ZX296702_SPDIF1_PCLK 12 177*4882a593Smuzhiyun #define ZX296702_SPDIF1_DIV 13 178*4882a593Smuzhiyun #define ZX296702_LSP1CLK_END 14 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_ZX296702_H */ 181