1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides clock numbers for the ingenic,x1830-cgu DT binding. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * They are roughly ordered as: 6*4882a593Smuzhiyun * - external clocks 7*4882a593Smuzhiyun * - PLLs 8*4882a593Smuzhiyun * - muxes/dividers in the order they appear in the x1830 programmers manual 9*4882a593Smuzhiyun * - gates in order of their bit in the CLKGR* registers 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__ 13*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_X1830_CGU_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define X1830_CLK_EXCLK 0 16*4882a593Smuzhiyun #define X1830_CLK_RTCLK 1 17*4882a593Smuzhiyun #define X1830_CLK_APLL 2 18*4882a593Smuzhiyun #define X1830_CLK_MPLL 3 19*4882a593Smuzhiyun #define X1830_CLK_EPLL 4 20*4882a593Smuzhiyun #define X1830_CLK_VPLL 5 21*4882a593Smuzhiyun #define X1830_CLK_OTGPHY 6 22*4882a593Smuzhiyun #define X1830_CLK_SCLKA 7 23*4882a593Smuzhiyun #define X1830_CLK_CPUMUX 8 24*4882a593Smuzhiyun #define X1830_CLK_CPU 9 25*4882a593Smuzhiyun #define X1830_CLK_L2CACHE 10 26*4882a593Smuzhiyun #define X1830_CLK_AHB0 11 27*4882a593Smuzhiyun #define X1830_CLK_AHB2PMUX 12 28*4882a593Smuzhiyun #define X1830_CLK_AHB2 13 29*4882a593Smuzhiyun #define X1830_CLK_PCLK 14 30*4882a593Smuzhiyun #define X1830_CLK_DDR 15 31*4882a593Smuzhiyun #define X1830_CLK_MAC 16 32*4882a593Smuzhiyun #define X1830_CLK_LCD 17 33*4882a593Smuzhiyun #define X1830_CLK_MSCMUX 18 34*4882a593Smuzhiyun #define X1830_CLK_MSC0 19 35*4882a593Smuzhiyun #define X1830_CLK_MSC1 20 36*4882a593Smuzhiyun #define X1830_CLK_SSIPLL 21 37*4882a593Smuzhiyun #define X1830_CLK_SSIPLL_DIV2 22 38*4882a593Smuzhiyun #define X1830_CLK_SSIMUX 23 39*4882a593Smuzhiyun #define X1830_CLK_EMC 24 40*4882a593Smuzhiyun #define X1830_CLK_EFUSE 25 41*4882a593Smuzhiyun #define X1830_CLK_OTG 26 42*4882a593Smuzhiyun #define X1830_CLK_SSI0 27 43*4882a593Smuzhiyun #define X1830_CLK_SMB0 28 44*4882a593Smuzhiyun #define X1830_CLK_SMB1 29 45*4882a593Smuzhiyun #define X1830_CLK_SMB2 30 46*4882a593Smuzhiyun #define X1830_CLK_UART0 31 47*4882a593Smuzhiyun #define X1830_CLK_UART1 32 48*4882a593Smuzhiyun #define X1830_CLK_SSI1 33 49*4882a593Smuzhiyun #define X1830_CLK_SFC 34 50*4882a593Smuzhiyun #define X1830_CLK_PDMA 35 51*4882a593Smuzhiyun #define X1830_CLK_TCU 36 52*4882a593Smuzhiyun #define X1830_CLK_DTRNG 37 53*4882a593Smuzhiyun #define X1830_CLK_OST 38 54*4882a593Smuzhiyun #define X1830_CLK_EXCLK_DIV512 39 55*4882a593Smuzhiyun #define X1830_CLK_RTC 40 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */ 58