1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_VF610_H 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_VF610_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define VF610_CLK_DUMMY 0 10*4882a593Smuzhiyun #define VF610_CLK_SIRC_128K 1 11*4882a593Smuzhiyun #define VF610_CLK_SIRC_32K 2 12*4882a593Smuzhiyun #define VF610_CLK_FIRC 3 13*4882a593Smuzhiyun #define VF610_CLK_SXOSC 4 14*4882a593Smuzhiyun #define VF610_CLK_FXOSC 5 15*4882a593Smuzhiyun #define VF610_CLK_FXOSC_HALF 6 16*4882a593Smuzhiyun #define VF610_CLK_SLOW_CLK_SEL 7 17*4882a593Smuzhiyun #define VF610_CLK_FASK_CLK_SEL 8 18*4882a593Smuzhiyun #define VF610_CLK_AUDIO_EXT 9 19*4882a593Smuzhiyun #define VF610_CLK_ENET_EXT 10 20*4882a593Smuzhiyun #define VF610_CLK_PLL1_SYS 11 21*4882a593Smuzhiyun #define VF610_CLK_PLL1_PFD1 12 22*4882a593Smuzhiyun #define VF610_CLK_PLL1_PFD2 13 23*4882a593Smuzhiyun #define VF610_CLK_PLL1_PFD3 14 24*4882a593Smuzhiyun #define VF610_CLK_PLL1_PFD4 15 25*4882a593Smuzhiyun #define VF610_CLK_PLL2_BUS 16 26*4882a593Smuzhiyun #define VF610_CLK_PLL2_PFD1 17 27*4882a593Smuzhiyun #define VF610_CLK_PLL2_PFD2 18 28*4882a593Smuzhiyun #define VF610_CLK_PLL2_PFD3 19 29*4882a593Smuzhiyun #define VF610_CLK_PLL2_PFD4 20 30*4882a593Smuzhiyun #define VF610_CLK_PLL3_USB_OTG 21 31*4882a593Smuzhiyun #define VF610_CLK_PLL3_PFD1 22 32*4882a593Smuzhiyun #define VF610_CLK_PLL3_PFD2 23 33*4882a593Smuzhiyun #define VF610_CLK_PLL3_PFD3 24 34*4882a593Smuzhiyun #define VF610_CLK_PLL3_PFD4 25 35*4882a593Smuzhiyun #define VF610_CLK_PLL4_AUDIO 26 36*4882a593Smuzhiyun #define VF610_CLK_PLL5_ENET 27 37*4882a593Smuzhiyun #define VF610_CLK_PLL6_VIDEO 28 38*4882a593Smuzhiyun #define VF610_CLK_PLL3_MAIN_DIV 29 39*4882a593Smuzhiyun #define VF610_CLK_PLL4_MAIN_DIV 30 40*4882a593Smuzhiyun #define VF610_CLK_PLL6_MAIN_DIV 31 41*4882a593Smuzhiyun #define VF610_CLK_PLL1_PFD_SEL 32 42*4882a593Smuzhiyun #define VF610_CLK_PLL2_PFD_SEL 33 43*4882a593Smuzhiyun #define VF610_CLK_SYS_SEL 34 44*4882a593Smuzhiyun #define VF610_CLK_DDR_SEL 35 45*4882a593Smuzhiyun #define VF610_CLK_SYS_BUS 36 46*4882a593Smuzhiyun #define VF610_CLK_PLATFORM_BUS 37 47*4882a593Smuzhiyun #define VF610_CLK_IPG_BUS 38 48*4882a593Smuzhiyun #define VF610_CLK_UART0 39 49*4882a593Smuzhiyun #define VF610_CLK_UART1 40 50*4882a593Smuzhiyun #define VF610_CLK_UART2 41 51*4882a593Smuzhiyun #define VF610_CLK_UART3 42 52*4882a593Smuzhiyun #define VF610_CLK_UART4 43 53*4882a593Smuzhiyun #define VF610_CLK_UART5 44 54*4882a593Smuzhiyun #define VF610_CLK_PIT 45 55*4882a593Smuzhiyun #define VF610_CLK_I2C0 46 56*4882a593Smuzhiyun #define VF610_CLK_I2C1 47 57*4882a593Smuzhiyun #define VF610_CLK_I2C2 48 58*4882a593Smuzhiyun #define VF610_CLK_I2C3 49 59*4882a593Smuzhiyun #define VF610_CLK_FTM0_EXT_SEL 50 60*4882a593Smuzhiyun #define VF610_CLK_FTM0_FIX_SEL 51 61*4882a593Smuzhiyun #define VF610_CLK_FTM0_EXT_FIX_EN 52 62*4882a593Smuzhiyun #define VF610_CLK_FTM1_EXT_SEL 53 63*4882a593Smuzhiyun #define VF610_CLK_FTM1_FIX_SEL 54 64*4882a593Smuzhiyun #define VF610_CLK_FTM1_EXT_FIX_EN 55 65*4882a593Smuzhiyun #define VF610_CLK_FTM2_EXT_SEL 56 66*4882a593Smuzhiyun #define VF610_CLK_FTM2_FIX_SEL 57 67*4882a593Smuzhiyun #define VF610_CLK_FTM2_EXT_FIX_EN 58 68*4882a593Smuzhiyun #define VF610_CLK_FTM3_EXT_SEL 59 69*4882a593Smuzhiyun #define VF610_CLK_FTM3_FIX_SEL 60 70*4882a593Smuzhiyun #define VF610_CLK_FTM3_EXT_FIX_EN 61 71*4882a593Smuzhiyun #define VF610_CLK_FTM0 62 72*4882a593Smuzhiyun #define VF610_CLK_FTM1 63 73*4882a593Smuzhiyun #define VF610_CLK_FTM2 64 74*4882a593Smuzhiyun #define VF610_CLK_FTM3 65 75*4882a593Smuzhiyun #define VF610_CLK_ENET_50M 66 76*4882a593Smuzhiyun #define VF610_CLK_ENET_25M 67 77*4882a593Smuzhiyun #define VF610_CLK_ENET_SEL 68 78*4882a593Smuzhiyun #define VF610_CLK_ENET 69 79*4882a593Smuzhiyun #define VF610_CLK_ENET_TS_SEL 70 80*4882a593Smuzhiyun #define VF610_CLK_ENET_TS 71 81*4882a593Smuzhiyun #define VF610_CLK_DSPI0 72 82*4882a593Smuzhiyun #define VF610_CLK_DSPI1 73 83*4882a593Smuzhiyun #define VF610_CLK_DSPI2 74 84*4882a593Smuzhiyun #define VF610_CLK_DSPI3 75 85*4882a593Smuzhiyun #define VF610_CLK_WDT 76 86*4882a593Smuzhiyun #define VF610_CLK_ESDHC0_SEL 77 87*4882a593Smuzhiyun #define VF610_CLK_ESDHC0_EN 78 88*4882a593Smuzhiyun #define VF610_CLK_ESDHC0_DIV 79 89*4882a593Smuzhiyun #define VF610_CLK_ESDHC0 80 90*4882a593Smuzhiyun #define VF610_CLK_ESDHC1_SEL 81 91*4882a593Smuzhiyun #define VF610_CLK_ESDHC1_EN 82 92*4882a593Smuzhiyun #define VF610_CLK_ESDHC1_DIV 83 93*4882a593Smuzhiyun #define VF610_CLK_ESDHC1 84 94*4882a593Smuzhiyun #define VF610_CLK_DCU0_SEL 85 95*4882a593Smuzhiyun #define VF610_CLK_DCU0_EN 86 96*4882a593Smuzhiyun #define VF610_CLK_DCU0_DIV 87 97*4882a593Smuzhiyun #define VF610_CLK_DCU0 88 98*4882a593Smuzhiyun #define VF610_CLK_DCU1_SEL 89 99*4882a593Smuzhiyun #define VF610_CLK_DCU1_EN 90 100*4882a593Smuzhiyun #define VF610_CLK_DCU1_DIV 91 101*4882a593Smuzhiyun #define VF610_CLK_DCU1 92 102*4882a593Smuzhiyun #define VF610_CLK_ESAI_SEL 93 103*4882a593Smuzhiyun #define VF610_CLK_ESAI_EN 94 104*4882a593Smuzhiyun #define VF610_CLK_ESAI_DIV 95 105*4882a593Smuzhiyun #define VF610_CLK_ESAI 96 106*4882a593Smuzhiyun #define VF610_CLK_SAI0_SEL 97 107*4882a593Smuzhiyun #define VF610_CLK_SAI0_EN 98 108*4882a593Smuzhiyun #define VF610_CLK_SAI0_DIV 99 109*4882a593Smuzhiyun #define VF610_CLK_SAI0 100 110*4882a593Smuzhiyun #define VF610_CLK_SAI1_SEL 101 111*4882a593Smuzhiyun #define VF610_CLK_SAI1_EN 102 112*4882a593Smuzhiyun #define VF610_CLK_SAI1_DIV 103 113*4882a593Smuzhiyun #define VF610_CLK_SAI1 104 114*4882a593Smuzhiyun #define VF610_CLK_SAI2_SEL 105 115*4882a593Smuzhiyun #define VF610_CLK_SAI2_EN 106 116*4882a593Smuzhiyun #define VF610_CLK_SAI2_DIV 107 117*4882a593Smuzhiyun #define VF610_CLK_SAI2 108 118*4882a593Smuzhiyun #define VF610_CLK_SAI3_SEL 109 119*4882a593Smuzhiyun #define VF610_CLK_SAI3_EN 110 120*4882a593Smuzhiyun #define VF610_CLK_SAI3_DIV 111 121*4882a593Smuzhiyun #define VF610_CLK_SAI3 112 122*4882a593Smuzhiyun #define VF610_CLK_USBC0 113 123*4882a593Smuzhiyun #define VF610_CLK_USBC1 114 124*4882a593Smuzhiyun #define VF610_CLK_QSPI0_SEL 115 125*4882a593Smuzhiyun #define VF610_CLK_QSPI0_EN 116 126*4882a593Smuzhiyun #define VF610_CLK_QSPI0_X4_DIV 117 127*4882a593Smuzhiyun #define VF610_CLK_QSPI0_X2_DIV 118 128*4882a593Smuzhiyun #define VF610_CLK_QSPI0_X1_DIV 119 129*4882a593Smuzhiyun #define VF610_CLK_QSPI1_SEL 120 130*4882a593Smuzhiyun #define VF610_CLK_QSPI1_EN 121 131*4882a593Smuzhiyun #define VF610_CLK_QSPI1_X4_DIV 122 132*4882a593Smuzhiyun #define VF610_CLK_QSPI1_X2_DIV 123 133*4882a593Smuzhiyun #define VF610_CLK_QSPI1_X1_DIV 124 134*4882a593Smuzhiyun #define VF610_CLK_QSPI0 125 135*4882a593Smuzhiyun #define VF610_CLK_QSPI1 126 136*4882a593Smuzhiyun #define VF610_CLK_NFC_SEL 127 137*4882a593Smuzhiyun #define VF610_CLK_NFC_EN 128 138*4882a593Smuzhiyun #define VF610_CLK_NFC_PRE_DIV 129 139*4882a593Smuzhiyun #define VF610_CLK_NFC_FRAC_DIV 130 140*4882a593Smuzhiyun #define VF610_CLK_NFC_INV 131 141*4882a593Smuzhiyun #define VF610_CLK_NFC 132 142*4882a593Smuzhiyun #define VF610_CLK_VADC_SEL 133 143*4882a593Smuzhiyun #define VF610_CLK_VADC_EN 134 144*4882a593Smuzhiyun #define VF610_CLK_VADC_DIV 135 145*4882a593Smuzhiyun #define VF610_CLK_VADC_DIV_HALF 136 146*4882a593Smuzhiyun #define VF610_CLK_VADC 137 147*4882a593Smuzhiyun #define VF610_CLK_ADC0 138 148*4882a593Smuzhiyun #define VF610_CLK_ADC1 139 149*4882a593Smuzhiyun #define VF610_CLK_DAC0 140 150*4882a593Smuzhiyun #define VF610_CLK_DAC1 141 151*4882a593Smuzhiyun #define VF610_CLK_FLEXCAN0 142 152*4882a593Smuzhiyun #define VF610_CLK_FLEXCAN1 143 153*4882a593Smuzhiyun #define VF610_CLK_ASRC 144 154*4882a593Smuzhiyun #define VF610_CLK_GPU_SEL 145 155*4882a593Smuzhiyun #define VF610_CLK_GPU_EN 146 156*4882a593Smuzhiyun #define VF610_CLK_GPU2D 147 157*4882a593Smuzhiyun #define VF610_CLK_ENET0 148 158*4882a593Smuzhiyun #define VF610_CLK_ENET1 149 159*4882a593Smuzhiyun #define VF610_CLK_DMAMUX0 150 160*4882a593Smuzhiyun #define VF610_CLK_DMAMUX1 151 161*4882a593Smuzhiyun #define VF610_CLK_DMAMUX2 152 162*4882a593Smuzhiyun #define VF610_CLK_DMAMUX3 153 163*4882a593Smuzhiyun #define VF610_CLK_FLEXCAN0_EN 154 164*4882a593Smuzhiyun #define VF610_CLK_FLEXCAN1_EN 155 165*4882a593Smuzhiyun #define VF610_CLK_PLL7_USB_HOST 156 166*4882a593Smuzhiyun #define VF610_CLK_USBPHY0 157 167*4882a593Smuzhiyun #define VF610_CLK_USBPHY1 158 168*4882a593Smuzhiyun #define VF610_CLK_LVDS1_IN 159 169*4882a593Smuzhiyun #define VF610_CLK_ANACLK1 160 170*4882a593Smuzhiyun #define VF610_CLK_PLL1_BYPASS_SRC 161 171*4882a593Smuzhiyun #define VF610_CLK_PLL2_BYPASS_SRC 162 172*4882a593Smuzhiyun #define VF610_CLK_PLL3_BYPASS_SRC 163 173*4882a593Smuzhiyun #define VF610_CLK_PLL4_BYPASS_SRC 164 174*4882a593Smuzhiyun #define VF610_CLK_PLL5_BYPASS_SRC 165 175*4882a593Smuzhiyun #define VF610_CLK_PLL6_BYPASS_SRC 166 176*4882a593Smuzhiyun #define VF610_CLK_PLL7_BYPASS_SRC 167 177*4882a593Smuzhiyun #define VF610_CLK_PLL1 168 178*4882a593Smuzhiyun #define VF610_CLK_PLL2 169 179*4882a593Smuzhiyun #define VF610_CLK_PLL3 170 180*4882a593Smuzhiyun #define VF610_CLK_PLL4 171 181*4882a593Smuzhiyun #define VF610_CLK_PLL5 172 182*4882a593Smuzhiyun #define VF610_CLK_PLL6 173 183*4882a593Smuzhiyun #define VF610_CLK_PLL7 174 184*4882a593Smuzhiyun #define VF610_PLL1_BYPASS 175 185*4882a593Smuzhiyun #define VF610_PLL2_BYPASS 176 186*4882a593Smuzhiyun #define VF610_PLL3_BYPASS 177 187*4882a593Smuzhiyun #define VF610_PLL4_BYPASS 178 188*4882a593Smuzhiyun #define VF610_PLL5_BYPASS 179 189*4882a593Smuzhiyun #define VF610_PLL6_BYPASS 180 190*4882a593Smuzhiyun #define VF610_PLL7_BYPASS 181 191*4882a593Smuzhiyun #define VF610_CLK_SNVS 182 192*4882a593Smuzhiyun #define VF610_CLK_DAP 183 193*4882a593Smuzhiyun #define VF610_CLK_OCOTP 184 194*4882a593Smuzhiyun #define VF610_CLK_DDRMC 185 195*4882a593Smuzhiyun #define VF610_CLK_WKPU 186 196*4882a593Smuzhiyun #define VF610_CLK_TCON0 187 197*4882a593Smuzhiyun #define VF610_CLK_TCON1 188 198*4882a593Smuzhiyun #define VF610_CLK_CAAM 189 199*4882a593Smuzhiyun #define VF610_CLK_CRC 190 200*4882a593Smuzhiyun #define VF610_CLK_END 191 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_VF610_H */ 203