1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants for binding nvidia,tegra30-car. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 6*4882a593Smuzhiyun * registers. These IDs often match those in the CAR's RST_DEVICES registers, 7*4882a593Smuzhiyun * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 8*4882a593Smuzhiyun * this case, those clocks are assigned IDs above 160 in order to highlight 9*4882a593Smuzhiyun * this issue. Implementations that interpret these clock IDs as bit values 10*4882a593Smuzhiyun * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 11*4882a593Smuzhiyun * explicitly handle these special cases. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * The balance of the clocks controlled by the CAR are assigned IDs of 160 and 14*4882a593Smuzhiyun * above. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 18*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define TEGRA30_CLK_CPU 0 21*4882a593Smuzhiyun /* 1 */ 22*4882a593Smuzhiyun /* 2 */ 23*4882a593Smuzhiyun /* 3 */ 24*4882a593Smuzhiyun #define TEGRA30_CLK_RTC 4 25*4882a593Smuzhiyun #define TEGRA30_CLK_TIMER 5 26*4882a593Smuzhiyun #define TEGRA30_CLK_UARTA 6 27*4882a593Smuzhiyun /* 7 (register bit affects uartb and vfir) */ 28*4882a593Smuzhiyun #define TEGRA30_CLK_GPIO 8 29*4882a593Smuzhiyun #define TEGRA30_CLK_SDMMC2 9 30*4882a593Smuzhiyun /* 10 (register bit affects spdif_in and spdif_out) */ 31*4882a593Smuzhiyun #define TEGRA30_CLK_I2S1 11 32*4882a593Smuzhiyun #define TEGRA30_CLK_I2C1 12 33*4882a593Smuzhiyun #define TEGRA30_CLK_NDFLASH 13 34*4882a593Smuzhiyun #define TEGRA30_CLK_SDMMC1 14 35*4882a593Smuzhiyun #define TEGRA30_CLK_SDMMC4 15 36*4882a593Smuzhiyun /* 16 */ 37*4882a593Smuzhiyun #define TEGRA30_CLK_PWM 17 38*4882a593Smuzhiyun #define TEGRA30_CLK_I2S2 18 39*4882a593Smuzhiyun #define TEGRA30_CLK_EPP 19 40*4882a593Smuzhiyun /* 20 (register bit affects vi and vi_sensor) */ 41*4882a593Smuzhiyun #define TEGRA30_CLK_GR2D 21 42*4882a593Smuzhiyun #define TEGRA30_CLK_USBD 22 43*4882a593Smuzhiyun #define TEGRA30_CLK_ISP 23 44*4882a593Smuzhiyun #define TEGRA30_CLK_GR3D 24 45*4882a593Smuzhiyun /* 25 */ 46*4882a593Smuzhiyun #define TEGRA30_CLK_DISP2 26 47*4882a593Smuzhiyun #define TEGRA30_CLK_DISP1 27 48*4882a593Smuzhiyun #define TEGRA30_CLK_HOST1X 28 49*4882a593Smuzhiyun #define TEGRA30_CLK_VCP 29 50*4882a593Smuzhiyun #define TEGRA30_CLK_I2S0 30 51*4882a593Smuzhiyun #define TEGRA30_CLK_COP_CACHE 31 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define TEGRA30_CLK_MC 32 54*4882a593Smuzhiyun #define TEGRA30_CLK_AHBDMA 33 55*4882a593Smuzhiyun #define TEGRA30_CLK_APBDMA 34 56*4882a593Smuzhiyun /* 35 */ 57*4882a593Smuzhiyun #define TEGRA30_CLK_KBC 36 58*4882a593Smuzhiyun #define TEGRA30_CLK_STATMON 37 59*4882a593Smuzhiyun #define TEGRA30_CLK_PMC 38 60*4882a593Smuzhiyun /* 39 (register bit affects fuse and fuse_burn) */ 61*4882a593Smuzhiyun #define TEGRA30_CLK_KFUSE 40 62*4882a593Smuzhiyun #define TEGRA30_CLK_SBC1 41 63*4882a593Smuzhiyun #define TEGRA30_CLK_NOR 42 64*4882a593Smuzhiyun /* 43 */ 65*4882a593Smuzhiyun #define TEGRA30_CLK_SBC2 44 66*4882a593Smuzhiyun /* 45 */ 67*4882a593Smuzhiyun #define TEGRA30_CLK_SBC3 46 68*4882a593Smuzhiyun #define TEGRA30_CLK_I2C5 47 69*4882a593Smuzhiyun #define TEGRA30_CLK_DSIA 48 70*4882a593Smuzhiyun /* 49 (register bit affects cve and tvo) */ 71*4882a593Smuzhiyun #define TEGRA30_CLK_MIPI 50 72*4882a593Smuzhiyun #define TEGRA30_CLK_HDMI 51 73*4882a593Smuzhiyun #define TEGRA30_CLK_CSI 52 74*4882a593Smuzhiyun #define TEGRA30_CLK_TVDAC 53 75*4882a593Smuzhiyun #define TEGRA30_CLK_I2C2 54 76*4882a593Smuzhiyun #define TEGRA30_CLK_UARTC 55 77*4882a593Smuzhiyun /* 56 */ 78*4882a593Smuzhiyun #define TEGRA30_CLK_EMC 57 79*4882a593Smuzhiyun #define TEGRA30_CLK_USB2 58 80*4882a593Smuzhiyun #define TEGRA30_CLK_USB3 59 81*4882a593Smuzhiyun #define TEGRA30_CLK_MPE 60 82*4882a593Smuzhiyun #define TEGRA30_CLK_VDE 61 83*4882a593Smuzhiyun #define TEGRA30_CLK_BSEA 62 84*4882a593Smuzhiyun #define TEGRA30_CLK_BSEV 63 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define TEGRA30_CLK_SPEEDO 64 87*4882a593Smuzhiyun #define TEGRA30_CLK_UARTD 65 88*4882a593Smuzhiyun #define TEGRA30_CLK_UARTE 66 89*4882a593Smuzhiyun #define TEGRA30_CLK_I2C3 67 90*4882a593Smuzhiyun #define TEGRA30_CLK_SBC4 68 91*4882a593Smuzhiyun #define TEGRA30_CLK_SDMMC3 69 92*4882a593Smuzhiyun #define TEGRA30_CLK_PCIE 70 93*4882a593Smuzhiyun #define TEGRA30_CLK_OWR 71 94*4882a593Smuzhiyun #define TEGRA30_CLK_AFI 72 95*4882a593Smuzhiyun #define TEGRA30_CLK_CSITE 73 96*4882a593Smuzhiyun /* 74 */ 97*4882a593Smuzhiyun #define TEGRA30_CLK_AVPUCQ 75 98*4882a593Smuzhiyun #define TEGRA30_CLK_LA 76 99*4882a593Smuzhiyun /* 77 */ 100*4882a593Smuzhiyun /* 78 */ 101*4882a593Smuzhiyun #define TEGRA30_CLK_DTV 79 102*4882a593Smuzhiyun #define TEGRA30_CLK_NDSPEED 80 103*4882a593Smuzhiyun #define TEGRA30_CLK_I2CSLOW 81 104*4882a593Smuzhiyun #define TEGRA30_CLK_DSIB 82 105*4882a593Smuzhiyun /* 83 */ 106*4882a593Smuzhiyun #define TEGRA30_CLK_IRAMA 84 107*4882a593Smuzhiyun #define TEGRA30_CLK_IRAMB 85 108*4882a593Smuzhiyun #define TEGRA30_CLK_IRAMC 86 109*4882a593Smuzhiyun #define TEGRA30_CLK_IRAMD 87 110*4882a593Smuzhiyun #define TEGRA30_CLK_CRAM2 88 111*4882a593Smuzhiyun /* 89 */ 112*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ 113*4882a593Smuzhiyun /* 91 */ 114*4882a593Smuzhiyun #define TEGRA30_CLK_CSUS 92 115*4882a593Smuzhiyun #define TEGRA30_CLK_CDEV2 93 116*4882a593Smuzhiyun #define TEGRA30_CLK_CDEV1 94 117*4882a593Smuzhiyun /* 95 */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define TEGRA30_CLK_CPU_G 96 120*4882a593Smuzhiyun #define TEGRA30_CLK_CPU_LP 97 121*4882a593Smuzhiyun #define TEGRA30_CLK_GR3D2 98 122*4882a593Smuzhiyun #define TEGRA30_CLK_MSELECT 99 123*4882a593Smuzhiyun #define TEGRA30_CLK_TSENSOR 100 124*4882a593Smuzhiyun #define TEGRA30_CLK_I2S3 101 125*4882a593Smuzhiyun #define TEGRA30_CLK_I2S4 102 126*4882a593Smuzhiyun #define TEGRA30_CLK_I2C4 103 127*4882a593Smuzhiyun #define TEGRA30_CLK_SBC5 104 128*4882a593Smuzhiyun #define TEGRA30_CLK_SBC6 105 129*4882a593Smuzhiyun #define TEGRA30_CLK_D_AUDIO 106 130*4882a593Smuzhiyun #define TEGRA30_CLK_APBIF 107 131*4882a593Smuzhiyun #define TEGRA30_CLK_DAM0 108 132*4882a593Smuzhiyun #define TEGRA30_CLK_DAM1 109 133*4882a593Smuzhiyun #define TEGRA30_CLK_DAM2 110 134*4882a593Smuzhiyun #define TEGRA30_CLK_HDA2CODEC_2X 111 135*4882a593Smuzhiyun #define TEGRA30_CLK_ATOMICS 112 136*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO0_2X 113 137*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO1_2X 114 138*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO2_2X 115 139*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO3_2X 116 140*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO4_2X 117 141*4882a593Smuzhiyun #define TEGRA30_CLK_SPDIF_2X 118 142*4882a593Smuzhiyun #define TEGRA30_CLK_ACTMON 119 143*4882a593Smuzhiyun #define TEGRA30_CLK_EXTERN1 120 144*4882a593Smuzhiyun #define TEGRA30_CLK_EXTERN2 121 145*4882a593Smuzhiyun #define TEGRA30_CLK_EXTERN3 122 146*4882a593Smuzhiyun #define TEGRA30_CLK_SATA_OOB 123 147*4882a593Smuzhiyun #define TEGRA30_CLK_SATA 124 148*4882a593Smuzhiyun #define TEGRA30_CLK_HDA 125 149*4882a593Smuzhiyun /* 126 */ 150*4882a593Smuzhiyun #define TEGRA30_CLK_SE 127 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define TEGRA30_CLK_HDA2HDMI 128 153*4882a593Smuzhiyun #define TEGRA30_CLK_SATA_COLD 129 154*4882a593Smuzhiyun /* 130 */ 155*4882a593Smuzhiyun /* 131 */ 156*4882a593Smuzhiyun /* 132 */ 157*4882a593Smuzhiyun /* 133 */ 158*4882a593Smuzhiyun /* 134 */ 159*4882a593Smuzhiyun /* 135 */ 160*4882a593Smuzhiyun #define TEGRA30_CLK_CEC 136 161*4882a593Smuzhiyun /* 137 */ 162*4882a593Smuzhiyun /* 138 */ 163*4882a593Smuzhiyun /* 139 */ 164*4882a593Smuzhiyun /* 140 */ 165*4882a593Smuzhiyun /* 141 */ 166*4882a593Smuzhiyun /* 142 */ 167*4882a593Smuzhiyun /* 143 */ 168*4882a593Smuzhiyun /* 144 */ 169*4882a593Smuzhiyun /* 145 */ 170*4882a593Smuzhiyun /* 146 */ 171*4882a593Smuzhiyun /* 147 */ 172*4882a593Smuzhiyun /* 148 */ 173*4882a593Smuzhiyun /* 149 */ 174*4882a593Smuzhiyun /* 150 */ 175*4882a593Smuzhiyun /* 151 */ 176*4882a593Smuzhiyun /* 152 */ 177*4882a593Smuzhiyun /* 153 */ 178*4882a593Smuzhiyun /* 154 */ 179*4882a593Smuzhiyun /* 155 */ 180*4882a593Smuzhiyun /* 156 */ 181*4882a593Smuzhiyun /* 157 */ 182*4882a593Smuzhiyun /* 158 */ 183*4882a593Smuzhiyun /* 159 */ 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #define TEGRA30_CLK_UARTB 160 186*4882a593Smuzhiyun #define TEGRA30_CLK_VFIR 161 187*4882a593Smuzhiyun #define TEGRA30_CLK_SPDIF_IN 162 188*4882a593Smuzhiyun #define TEGRA30_CLK_SPDIF_OUT 163 189*4882a593Smuzhiyun #define TEGRA30_CLK_VI 164 190*4882a593Smuzhiyun #define TEGRA30_CLK_VI_SENSOR 165 191*4882a593Smuzhiyun #define TEGRA30_CLK_FUSE 166 192*4882a593Smuzhiyun #define TEGRA30_CLK_FUSE_BURN 167 193*4882a593Smuzhiyun #define TEGRA30_CLK_CVE 168 194*4882a593Smuzhiyun #define TEGRA30_CLK_TVO 169 195*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_32K 170 196*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_M 171 197*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_M_DIV2 172 198*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_M_DIV4 173 199*4882a593Smuzhiyun #define TEGRA30_CLK_OSC_DIV2 172 200*4882a593Smuzhiyun #define TEGRA30_CLK_OSC_DIV4 173 201*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_REF 174 202*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_C 175 203*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_C_OUT1 176 204*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_M 177 205*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_M_OUT1 178 206*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_P 179 207*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_P_OUT1 180 208*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_P_OUT2 181 209*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_P_OUT3 182 210*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_P_OUT4 183 211*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_A 184 212*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_A_OUT0 185 213*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_D 186 214*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_D_OUT0 187 215*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_D2 188 216*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_D2_OUT0 189 217*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_U 190 218*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_X 191 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_X_OUT0 192 221*4882a593Smuzhiyun #define TEGRA30_CLK_PLL_E 193 222*4882a593Smuzhiyun #define TEGRA30_CLK_SPDIF_IN_SYNC 194 223*4882a593Smuzhiyun #define TEGRA30_CLK_I2S0_SYNC 195 224*4882a593Smuzhiyun #define TEGRA30_CLK_I2S1_SYNC 196 225*4882a593Smuzhiyun #define TEGRA30_CLK_I2S2_SYNC 197 226*4882a593Smuzhiyun #define TEGRA30_CLK_I2S3_SYNC 198 227*4882a593Smuzhiyun #define TEGRA30_CLK_I2S4_SYNC 199 228*4882a593Smuzhiyun #define TEGRA30_CLK_VIMCLK_SYNC 200 229*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO0 201 230*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO1 202 231*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO2 203 232*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO3 204 233*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO4 205 234*4882a593Smuzhiyun #define TEGRA30_CLK_SPDIF 206 235*4882a593Smuzhiyun /* 207 */ 236*4882a593Smuzhiyun /* 208 */ 237*4882a593Smuzhiyun /* 209 */ 238*4882a593Smuzhiyun #define TEGRA30_CLK_SCLK 210 239*4882a593Smuzhiyun /* 211 */ 240*4882a593Smuzhiyun #define TEGRA30_CLK_CCLK_G 212 241*4882a593Smuzhiyun #define TEGRA30_CLK_CCLK_LP 213 242*4882a593Smuzhiyun #define TEGRA30_CLK_TWD 214 243*4882a593Smuzhiyun #define TEGRA30_CLK_CML0 215 244*4882a593Smuzhiyun #define TEGRA30_CLK_CML1 216 245*4882a593Smuzhiyun #define TEGRA30_CLK_HCLK 217 246*4882a593Smuzhiyun #define TEGRA30_CLK_PCLK 218 247*4882a593Smuzhiyun /* 219 */ 248*4882a593Smuzhiyun #define TEGRA30_CLK_OSC 220 249*4882a593Smuzhiyun /* 221 */ 250*4882a593Smuzhiyun /* 222 */ 251*4882a593Smuzhiyun /* 223 */ 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun /* 288 */ 254*4882a593Smuzhiyun /* 289 */ 255*4882a593Smuzhiyun /* 290 */ 256*4882a593Smuzhiyun /* 291 */ 257*4882a593Smuzhiyun /* 292 */ 258*4882a593Smuzhiyun /* 293 */ 259*4882a593Smuzhiyun /* 294 */ 260*4882a593Smuzhiyun /* 295 */ 261*4882a593Smuzhiyun /* 296 */ 262*4882a593Smuzhiyun /* 297 */ 263*4882a593Smuzhiyun /* 298 */ 264*4882a593Smuzhiyun /* 299 */ 265*4882a593Smuzhiyun /* 300 */ 266*4882a593Smuzhiyun /* 301 */ 267*4882a593Smuzhiyun /* 302 */ 268*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO0_MUX 303 269*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO1_MUX 304 270*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO2_MUX 305 271*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO3_MUX 306 272*4882a593Smuzhiyun #define TEGRA30_CLK_AUDIO4_MUX 307 273*4882a593Smuzhiyun #define TEGRA30_CLK_SPDIF_MUX 308 274*4882a593Smuzhiyun #define TEGRA30_CLK_CLK_MAX 309 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ 277