1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 5*4882a593Smuzhiyun #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /** @brief output of gate CLK_ENB_FUSE */ 8*4882a593Smuzhiyun #define TEGRA234_CLK_FUSE 40 9*4882a593Smuzhiyun /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 10*4882a593Smuzhiyun #define TEGRA234_CLK_SDMMC4 123 11*4882a593Smuzhiyun /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 12*4882a593Smuzhiyun #define TEGRA234_CLK_UARTA 155 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #endif 15