1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants for binding nvidia,tegra124-car or 4*4882a593Smuzhiyun * nvidia,tegra132-car. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 7*4882a593Smuzhiyun * registers. These IDs often match those in the CAR's RST_DEVICES registers, 8*4882a593Smuzhiyun * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 9*4882a593Smuzhiyun * this case, those clocks are assigned IDs above 185 in order to highlight 10*4882a593Smuzhiyun * this issue. Implementations that interpret these clock IDs as bit values 11*4882a593Smuzhiyun * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 12*4882a593Smuzhiyun * explicitly handle these special cases. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * The balance of the clocks controlled by the CAR are assigned IDs of 185 and 15*4882a593Smuzhiyun * above. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H 19*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 0 */ 22*4882a593Smuzhiyun /* 1 */ 23*4882a593Smuzhiyun /* 2 */ 24*4882a593Smuzhiyun #define TEGRA124_CLK_ISPB 3 25*4882a593Smuzhiyun #define TEGRA124_CLK_RTC 4 26*4882a593Smuzhiyun #define TEGRA124_CLK_TIMER 5 27*4882a593Smuzhiyun #define TEGRA124_CLK_UARTA 6 28*4882a593Smuzhiyun /* 7 (register bit affects uartb and vfir) */ 29*4882a593Smuzhiyun /* 8 */ 30*4882a593Smuzhiyun #define TEGRA124_CLK_SDMMC2 9 31*4882a593Smuzhiyun /* 10 (register bit affects spdif_in and spdif_out) */ 32*4882a593Smuzhiyun #define TEGRA124_CLK_I2S1 11 33*4882a593Smuzhiyun #define TEGRA124_CLK_I2C1 12 34*4882a593Smuzhiyun /* 13 */ 35*4882a593Smuzhiyun #define TEGRA124_CLK_SDMMC1 14 36*4882a593Smuzhiyun #define TEGRA124_CLK_SDMMC4 15 37*4882a593Smuzhiyun /* 16 */ 38*4882a593Smuzhiyun #define TEGRA124_CLK_PWM 17 39*4882a593Smuzhiyun #define TEGRA124_CLK_I2S2 18 40*4882a593Smuzhiyun /* 20 (register bit affects vi and vi_sensor) */ 41*4882a593Smuzhiyun /* 21 */ 42*4882a593Smuzhiyun #define TEGRA124_CLK_USBD 22 43*4882a593Smuzhiyun #define TEGRA124_CLK_ISP 23 44*4882a593Smuzhiyun /* 26 */ 45*4882a593Smuzhiyun /* 25 */ 46*4882a593Smuzhiyun #define TEGRA124_CLK_DISP2 26 47*4882a593Smuzhiyun #define TEGRA124_CLK_DISP1 27 48*4882a593Smuzhiyun #define TEGRA124_CLK_HOST1X 28 49*4882a593Smuzhiyun #define TEGRA124_CLK_VCP 29 50*4882a593Smuzhiyun #define TEGRA124_CLK_I2S0 30 51*4882a593Smuzhiyun /* 31 */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define TEGRA124_CLK_MC 32 54*4882a593Smuzhiyun /* 33 */ 55*4882a593Smuzhiyun #define TEGRA124_CLK_APBDMA 34 56*4882a593Smuzhiyun /* 35 */ 57*4882a593Smuzhiyun #define TEGRA124_CLK_KBC 36 58*4882a593Smuzhiyun /* 37 */ 59*4882a593Smuzhiyun /* 38 */ 60*4882a593Smuzhiyun /* 39 (register bit affects fuse and fuse_burn) */ 61*4882a593Smuzhiyun #define TEGRA124_CLK_KFUSE 40 62*4882a593Smuzhiyun #define TEGRA124_CLK_SBC1 41 63*4882a593Smuzhiyun #define TEGRA124_CLK_NOR 42 64*4882a593Smuzhiyun /* 43 */ 65*4882a593Smuzhiyun #define TEGRA124_CLK_SBC2 44 66*4882a593Smuzhiyun /* 45 */ 67*4882a593Smuzhiyun #define TEGRA124_CLK_SBC3 46 68*4882a593Smuzhiyun #define TEGRA124_CLK_I2C5 47 69*4882a593Smuzhiyun #define TEGRA124_CLK_DSIA 48 70*4882a593Smuzhiyun /* 49 */ 71*4882a593Smuzhiyun #define TEGRA124_CLK_MIPI 50 72*4882a593Smuzhiyun #define TEGRA124_CLK_HDMI 51 73*4882a593Smuzhiyun #define TEGRA124_CLK_CSI 52 74*4882a593Smuzhiyun /* 53 */ 75*4882a593Smuzhiyun #define TEGRA124_CLK_I2C2 54 76*4882a593Smuzhiyun #define TEGRA124_CLK_UARTC 55 77*4882a593Smuzhiyun #define TEGRA124_CLK_MIPI_CAL 56 78*4882a593Smuzhiyun #define TEGRA124_CLK_EMC 57 79*4882a593Smuzhiyun #define TEGRA124_CLK_USB2 58 80*4882a593Smuzhiyun #define TEGRA124_CLK_USB3 59 81*4882a593Smuzhiyun /* 60 */ 82*4882a593Smuzhiyun #define TEGRA124_CLK_VDE 61 83*4882a593Smuzhiyun #define TEGRA124_CLK_BSEA 62 84*4882a593Smuzhiyun #define TEGRA124_CLK_BSEV 63 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* 64 */ 87*4882a593Smuzhiyun #define TEGRA124_CLK_UARTD 65 88*4882a593Smuzhiyun /* 66 */ 89*4882a593Smuzhiyun #define TEGRA124_CLK_I2C3 67 90*4882a593Smuzhiyun #define TEGRA124_CLK_SBC4 68 91*4882a593Smuzhiyun #define TEGRA124_CLK_SDMMC3 69 92*4882a593Smuzhiyun #define TEGRA124_CLK_PCIE 70 93*4882a593Smuzhiyun #define TEGRA124_CLK_OWR 71 94*4882a593Smuzhiyun #define TEGRA124_CLK_AFI 72 95*4882a593Smuzhiyun #define TEGRA124_CLK_CSITE 73 96*4882a593Smuzhiyun /* 74 */ 97*4882a593Smuzhiyun /* 75 */ 98*4882a593Smuzhiyun #define TEGRA124_CLK_LA 76 99*4882a593Smuzhiyun #define TEGRA124_CLK_TRACE 77 100*4882a593Smuzhiyun #define TEGRA124_CLK_SOC_THERM 78 101*4882a593Smuzhiyun #define TEGRA124_CLK_DTV 79 102*4882a593Smuzhiyun /* 80 */ 103*4882a593Smuzhiyun #define TEGRA124_CLK_I2CSLOW 81 104*4882a593Smuzhiyun #define TEGRA124_CLK_DSIB 82 105*4882a593Smuzhiyun #define TEGRA124_CLK_TSEC 83 106*4882a593Smuzhiyun /* 84 */ 107*4882a593Smuzhiyun /* 85 */ 108*4882a593Smuzhiyun /* 86 */ 109*4882a593Smuzhiyun /* 87 */ 110*4882a593Smuzhiyun /* 88 */ 111*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_HOST 89 112*4882a593Smuzhiyun /* 90 */ 113*4882a593Smuzhiyun #define TEGRA124_CLK_MSENC 91 114*4882a593Smuzhiyun #define TEGRA124_CLK_CSUS 92 115*4882a593Smuzhiyun /* 93 */ 116*4882a593Smuzhiyun /* 94 */ 117*4882a593Smuzhiyun /* 95 (bit affects xusb_dev and xusb_dev_src) */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* 96 */ 120*4882a593Smuzhiyun /* 97 */ 121*4882a593Smuzhiyun /* 98 */ 122*4882a593Smuzhiyun #define TEGRA124_CLK_MSELECT 99 123*4882a593Smuzhiyun #define TEGRA124_CLK_TSENSOR 100 124*4882a593Smuzhiyun #define TEGRA124_CLK_I2S3 101 125*4882a593Smuzhiyun #define TEGRA124_CLK_I2S4 102 126*4882a593Smuzhiyun #define TEGRA124_CLK_I2C4 103 127*4882a593Smuzhiyun #define TEGRA124_CLK_SBC5 104 128*4882a593Smuzhiyun #define TEGRA124_CLK_SBC6 105 129*4882a593Smuzhiyun #define TEGRA124_CLK_D_AUDIO 106 130*4882a593Smuzhiyun #define TEGRA124_CLK_APBIF 107 131*4882a593Smuzhiyun #define TEGRA124_CLK_DAM0 108 132*4882a593Smuzhiyun #define TEGRA124_CLK_DAM1 109 133*4882a593Smuzhiyun #define TEGRA124_CLK_DAM2 110 134*4882a593Smuzhiyun #define TEGRA124_CLK_HDA2CODEC_2X 111 135*4882a593Smuzhiyun /* 112 */ 136*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO0_2X 113 137*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO1_2X 114 138*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO2_2X 115 139*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO3_2X 116 140*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO4_2X 117 141*4882a593Smuzhiyun #define TEGRA124_CLK_SPDIF_2X 118 142*4882a593Smuzhiyun #define TEGRA124_CLK_ACTMON 119 143*4882a593Smuzhiyun #define TEGRA124_CLK_EXTERN1 120 144*4882a593Smuzhiyun #define TEGRA124_CLK_EXTERN2 121 145*4882a593Smuzhiyun #define TEGRA124_CLK_EXTERN3 122 146*4882a593Smuzhiyun #define TEGRA124_CLK_SATA_OOB 123 147*4882a593Smuzhiyun #define TEGRA124_CLK_SATA 124 148*4882a593Smuzhiyun #define TEGRA124_CLK_HDA 125 149*4882a593Smuzhiyun /* 126 */ 150*4882a593Smuzhiyun #define TEGRA124_CLK_SE 127 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define TEGRA124_CLK_HDA2HDMI 128 153*4882a593Smuzhiyun #define TEGRA124_CLK_SATA_COLD 129 154*4882a593Smuzhiyun /* 130 */ 155*4882a593Smuzhiyun /* 131 */ 156*4882a593Smuzhiyun /* 132 */ 157*4882a593Smuzhiyun /* 133 */ 158*4882a593Smuzhiyun /* 134 */ 159*4882a593Smuzhiyun /* 135 */ 160*4882a593Smuzhiyun #define TEGRA124_CLK_CEC 136 161*4882a593Smuzhiyun /* 137 */ 162*4882a593Smuzhiyun /* 138 */ 163*4882a593Smuzhiyun /* 139 */ 164*4882a593Smuzhiyun /* 140 */ 165*4882a593Smuzhiyun /* 141 */ 166*4882a593Smuzhiyun /* 142 */ 167*4882a593Smuzhiyun /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ 168*4882a593Smuzhiyun /* xusb_host_src and xusb_ss_src) */ 169*4882a593Smuzhiyun #define TEGRA124_CLK_CILAB 144 170*4882a593Smuzhiyun #define TEGRA124_CLK_CILCD 145 171*4882a593Smuzhiyun #define TEGRA124_CLK_CILE 146 172*4882a593Smuzhiyun #define TEGRA124_CLK_DSIALP 147 173*4882a593Smuzhiyun #define TEGRA124_CLK_DSIBLP 148 174*4882a593Smuzhiyun #define TEGRA124_CLK_ENTROPY 149 175*4882a593Smuzhiyun #define TEGRA124_CLK_DDS 150 176*4882a593Smuzhiyun /* 151 */ 177*4882a593Smuzhiyun #define TEGRA124_CLK_DP2 152 178*4882a593Smuzhiyun #define TEGRA124_CLK_AMX 153 179*4882a593Smuzhiyun #define TEGRA124_CLK_ADX 154 180*4882a593Smuzhiyun /* 155 (bit affects dfll_ref and dfll_soc) */ 181*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_SS 156 182*4882a593Smuzhiyun /* 157 */ 183*4882a593Smuzhiyun /* 158 */ 184*4882a593Smuzhiyun /* 159 */ 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun /* 160 */ 187*4882a593Smuzhiyun /* 161 */ 188*4882a593Smuzhiyun /* 162 */ 189*4882a593Smuzhiyun /* 163 */ 190*4882a593Smuzhiyun /* 164 */ 191*4882a593Smuzhiyun /* 165 */ 192*4882a593Smuzhiyun #define TEGRA124_CLK_I2C6 166 193*4882a593Smuzhiyun /* 167 */ 194*4882a593Smuzhiyun /* 168 */ 195*4882a593Smuzhiyun /* 169 */ 196*4882a593Smuzhiyun /* 170 */ 197*4882a593Smuzhiyun #define TEGRA124_CLK_VIM2_CLK 171 198*4882a593Smuzhiyun /* 172 */ 199*4882a593Smuzhiyun /* 173 */ 200*4882a593Smuzhiyun /* 174 */ 201*4882a593Smuzhiyun /* 175 */ 202*4882a593Smuzhiyun #define TEGRA124_CLK_HDMI_AUDIO 176 203*4882a593Smuzhiyun #define TEGRA124_CLK_CLK72MHZ 177 204*4882a593Smuzhiyun #define TEGRA124_CLK_VIC03 178 205*4882a593Smuzhiyun /* 179 */ 206*4882a593Smuzhiyun #define TEGRA124_CLK_ADX1 180 207*4882a593Smuzhiyun #define TEGRA124_CLK_DPAUX 181 208*4882a593Smuzhiyun #define TEGRA124_CLK_SOR0 182 209*4882a593Smuzhiyun /* 183 */ 210*4882a593Smuzhiyun #define TEGRA124_CLK_GPU 184 211*4882a593Smuzhiyun #define TEGRA124_CLK_AMX1 185 212*4882a593Smuzhiyun /* 186 */ 213*4882a593Smuzhiyun /* 187 */ 214*4882a593Smuzhiyun /* 188 */ 215*4882a593Smuzhiyun /* 189 */ 216*4882a593Smuzhiyun /* 190 */ 217*4882a593Smuzhiyun /* 191 */ 218*4882a593Smuzhiyun #define TEGRA124_CLK_UARTB 192 219*4882a593Smuzhiyun #define TEGRA124_CLK_VFIR 193 220*4882a593Smuzhiyun #define TEGRA124_CLK_SPDIF_IN 194 221*4882a593Smuzhiyun #define TEGRA124_CLK_SPDIF_OUT 195 222*4882a593Smuzhiyun #define TEGRA124_CLK_VI 196 223*4882a593Smuzhiyun #define TEGRA124_CLK_VI_SENSOR 197 224*4882a593Smuzhiyun #define TEGRA124_CLK_FUSE 198 225*4882a593Smuzhiyun #define TEGRA124_CLK_FUSE_BURN 199 226*4882a593Smuzhiyun #define TEGRA124_CLK_CLK_32K 200 227*4882a593Smuzhiyun #define TEGRA124_CLK_CLK_M 201 228*4882a593Smuzhiyun #define TEGRA124_CLK_CLK_M_DIV2 202 229*4882a593Smuzhiyun #define TEGRA124_CLK_CLK_M_DIV4 203 230*4882a593Smuzhiyun #define TEGRA124_CLK_OSC_DIV2 202 231*4882a593Smuzhiyun #define TEGRA124_CLK_OSC_DIV4 203 232*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_REF 204 233*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_C 205 234*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_C_OUT1 206 235*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_C2 207 236*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_C3 208 237*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_M 209 238*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_M_OUT1 210 239*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_P 211 240*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_P_OUT1 212 241*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_P_OUT2 213 242*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_P_OUT3 214 243*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_P_OUT4 215 244*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_A 216 245*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_A_OUT0 217 246*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_D 218 247*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_D_OUT0 219 248*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_D2 220 249*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_D2_OUT0 221 250*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_U 222 251*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_U_480M 223 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_U_60M 224 254*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_U_48M 225 255*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_U_12M 226 256*4882a593Smuzhiyun /* 227 */ 257*4882a593Smuzhiyun /* 228 */ 258*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_RE_VCO 229 259*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_RE_OUT 230 260*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_E 231 261*4882a593Smuzhiyun #define TEGRA124_CLK_SPDIF_IN_SYNC 232 262*4882a593Smuzhiyun #define TEGRA124_CLK_I2S0_SYNC 233 263*4882a593Smuzhiyun #define TEGRA124_CLK_I2S1_SYNC 234 264*4882a593Smuzhiyun #define TEGRA124_CLK_I2S2_SYNC 235 265*4882a593Smuzhiyun #define TEGRA124_CLK_I2S3_SYNC 236 266*4882a593Smuzhiyun #define TEGRA124_CLK_I2S4_SYNC 237 267*4882a593Smuzhiyun #define TEGRA124_CLK_VIMCLK_SYNC 238 268*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO0 239 269*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO1 240 270*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO2 241 271*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO3 242 272*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO4 243 273*4882a593Smuzhiyun #define TEGRA124_CLK_SPDIF 244 274*4882a593Smuzhiyun /* 245 */ 275*4882a593Smuzhiyun /* 246 */ 276*4882a593Smuzhiyun /* 247 */ 277*4882a593Smuzhiyun /* 248 */ 278*4882a593Smuzhiyun #define TEGRA124_CLK_OSC 249 279*4882a593Smuzhiyun /* 250 */ 280*4882a593Smuzhiyun /* 251 */ 281*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_HOST_SRC 252 282*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_FALCON_SRC 253 283*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_FS_SRC 254 284*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_SS_SRC 255 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_DEV_SRC 256 287*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_DEV 257 288*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_HS_SRC 258 289*4882a593Smuzhiyun #define TEGRA124_CLK_SCLK 259 290*4882a593Smuzhiyun #define TEGRA124_CLK_HCLK 260 291*4882a593Smuzhiyun #define TEGRA124_CLK_PCLK 261 292*4882a593Smuzhiyun /* 262 */ 293*4882a593Smuzhiyun /* 263 */ 294*4882a593Smuzhiyun #define TEGRA124_CLK_DFLL_REF 264 295*4882a593Smuzhiyun #define TEGRA124_CLK_DFLL_SOC 265 296*4882a593Smuzhiyun #define TEGRA124_CLK_VI_SENSOR2 266 297*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_P_OUT5 267 298*4882a593Smuzhiyun #define TEGRA124_CLK_CML0 268 299*4882a593Smuzhiyun #define TEGRA124_CLK_CML1 269 300*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_C4 270 301*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_DP 271 302*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_E_MUX 272 303*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_D_DSI_OUT 273 304*4882a593Smuzhiyun /* 274 */ 305*4882a593Smuzhiyun /* 275 */ 306*4882a593Smuzhiyun /* 276 */ 307*4882a593Smuzhiyun /* 277 */ 308*4882a593Smuzhiyun /* 278 */ 309*4882a593Smuzhiyun /* 279 */ 310*4882a593Smuzhiyun /* 280 */ 311*4882a593Smuzhiyun /* 281 */ 312*4882a593Smuzhiyun /* 282 */ 313*4882a593Smuzhiyun /* 283 */ 314*4882a593Smuzhiyun /* 284 */ 315*4882a593Smuzhiyun /* 285 */ 316*4882a593Smuzhiyun /* 286 */ 317*4882a593Smuzhiyun /* 287 */ 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun /* 288 */ 320*4882a593Smuzhiyun /* 289 */ 321*4882a593Smuzhiyun /* 290 */ 322*4882a593Smuzhiyun /* 291 */ 323*4882a593Smuzhiyun /* 292 */ 324*4882a593Smuzhiyun /* 293 */ 325*4882a593Smuzhiyun /* 294 */ 326*4882a593Smuzhiyun /* 295 */ 327*4882a593Smuzhiyun /* 296 */ 328*4882a593Smuzhiyun /* 297 */ 329*4882a593Smuzhiyun /* 298 */ 330*4882a593Smuzhiyun /* 299 */ 331*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO0_MUX 300 332*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO1_MUX 301 333*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO2_MUX 302 334*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO3_MUX 303 335*4882a593Smuzhiyun #define TEGRA124_CLK_AUDIO4_MUX 304 336*4882a593Smuzhiyun #define TEGRA124_CLK_SPDIF_MUX 305 337*4882a593Smuzhiyun /* 306 */ 338*4882a593Smuzhiyun /* 307 */ 339*4882a593Smuzhiyun /* 308 */ 340*4882a593Smuzhiyun /* 309 */ 341*4882a593Smuzhiyun /* 310 */ 342*4882a593Smuzhiyun #define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */ 343*4882a593Smuzhiyun #define TEGRA124_CLK_SOR0_OUT 311 344*4882a593Smuzhiyun #define TEGRA124_CLK_XUSB_SS_DIV2 312 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_M_UD 313 347*4882a593Smuzhiyun #define TEGRA124_CLK_PLL_C_UD 314 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */ 350