1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define CLK_CPU 11 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CLK_BUS_DMA 14 13*4882a593Smuzhiyun #define CLK_BUS_MMC0 15 14*4882a593Smuzhiyun #define CLK_BUS_MMC1 16 15*4882a593Smuzhiyun #define CLK_BUS_DRAM 17 16*4882a593Smuzhiyun #define CLK_BUS_SPI0 18 17*4882a593Smuzhiyun #define CLK_BUS_SPI1 19 18*4882a593Smuzhiyun #define CLK_BUS_OTG 20 19*4882a593Smuzhiyun #define CLK_BUS_VE 21 20*4882a593Smuzhiyun #define CLK_BUS_LCD 22 21*4882a593Smuzhiyun #define CLK_BUS_DEINTERLACE 23 22*4882a593Smuzhiyun #define CLK_BUS_CSI 24 23*4882a593Smuzhiyun #define CLK_BUS_TVD 25 24*4882a593Smuzhiyun #define CLK_BUS_TVE 26 25*4882a593Smuzhiyun #define CLK_BUS_DE_BE 27 26*4882a593Smuzhiyun #define CLK_BUS_DE_FE 28 27*4882a593Smuzhiyun #define CLK_BUS_CODEC 29 28*4882a593Smuzhiyun #define CLK_BUS_SPDIF 30 29*4882a593Smuzhiyun #define CLK_BUS_IR 31 30*4882a593Smuzhiyun #define CLK_BUS_RSB 32 31*4882a593Smuzhiyun #define CLK_BUS_I2S0 33 32*4882a593Smuzhiyun #define CLK_BUS_I2C0 34 33*4882a593Smuzhiyun #define CLK_BUS_I2C1 35 34*4882a593Smuzhiyun #define CLK_BUS_I2C2 36 35*4882a593Smuzhiyun #define CLK_BUS_PIO 37 36*4882a593Smuzhiyun #define CLK_BUS_UART0 38 37*4882a593Smuzhiyun #define CLK_BUS_UART1 39 38*4882a593Smuzhiyun #define CLK_BUS_UART2 40 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define CLK_MMC0 41 41*4882a593Smuzhiyun #define CLK_MMC0_SAMPLE 42 42*4882a593Smuzhiyun #define CLK_MMC0_OUTPUT 43 43*4882a593Smuzhiyun #define CLK_MMC1 44 44*4882a593Smuzhiyun #define CLK_MMC1_SAMPLE 45 45*4882a593Smuzhiyun #define CLK_MMC1_OUTPUT 46 46*4882a593Smuzhiyun #define CLK_I2S 47 47*4882a593Smuzhiyun #define CLK_SPDIF 48 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define CLK_USB_PHY0 49 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define CLK_DRAM_VE 50 52*4882a593Smuzhiyun #define CLK_DRAM_CSI 51 53*4882a593Smuzhiyun #define CLK_DRAM_DEINTERLACE 52 54*4882a593Smuzhiyun #define CLK_DRAM_TVD 53 55*4882a593Smuzhiyun #define CLK_DRAM_DE_FE 54 56*4882a593Smuzhiyun #define CLK_DRAM_DE_BE 55 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define CLK_DE_BE 56 59*4882a593Smuzhiyun #define CLK_DE_FE 57 60*4882a593Smuzhiyun #define CLK_TCON 58 61*4882a593Smuzhiyun #define CLK_DEINTERLACE 59 62*4882a593Smuzhiyun #define CLK_TVE2_CLK 60 63*4882a593Smuzhiyun #define CLK_TVE1_CLK 61 64*4882a593Smuzhiyun #define CLK_TVD 62 65*4882a593Smuzhiyun #define CLK_CSI 63 66*4882a593Smuzhiyun #define CLK_VE 64 67*4882a593Smuzhiyun #define CLK_CODEC 65 68*4882a593Smuzhiyun #define CLK_AVS 66 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif 71