1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2016 Maxime Ripard 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Maxime Ripard <maxime.ripard@free-electrons.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_SUN5I_H_ 9*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_SUN5I_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CLK_HOSC 1 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CLK_PLL_VIDEO0_2X 9 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CLK_PLL_VIDEO1_2X 16 16*4882a593Smuzhiyun #define CLK_CPU 17 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CLK_AHB_OTG 23 19*4882a593Smuzhiyun #define CLK_AHB_EHCI 24 20*4882a593Smuzhiyun #define CLK_AHB_OHCI 25 21*4882a593Smuzhiyun #define CLK_AHB_SS 26 22*4882a593Smuzhiyun #define CLK_AHB_DMA 27 23*4882a593Smuzhiyun #define CLK_AHB_BIST 28 24*4882a593Smuzhiyun #define CLK_AHB_MMC0 29 25*4882a593Smuzhiyun #define CLK_AHB_MMC1 30 26*4882a593Smuzhiyun #define CLK_AHB_MMC2 31 27*4882a593Smuzhiyun #define CLK_AHB_NAND 32 28*4882a593Smuzhiyun #define CLK_AHB_SDRAM 33 29*4882a593Smuzhiyun #define CLK_AHB_EMAC 34 30*4882a593Smuzhiyun #define CLK_AHB_TS 35 31*4882a593Smuzhiyun #define CLK_AHB_SPI0 36 32*4882a593Smuzhiyun #define CLK_AHB_SPI1 37 33*4882a593Smuzhiyun #define CLK_AHB_SPI2 38 34*4882a593Smuzhiyun #define CLK_AHB_GPS 39 35*4882a593Smuzhiyun #define CLK_AHB_HSTIMER 40 36*4882a593Smuzhiyun #define CLK_AHB_VE 41 37*4882a593Smuzhiyun #define CLK_AHB_TVE 42 38*4882a593Smuzhiyun #define CLK_AHB_LCD 43 39*4882a593Smuzhiyun #define CLK_AHB_CSI 44 40*4882a593Smuzhiyun #define CLK_AHB_HDMI 45 41*4882a593Smuzhiyun #define CLK_AHB_DE_BE 46 42*4882a593Smuzhiyun #define CLK_AHB_DE_FE 47 43*4882a593Smuzhiyun #define CLK_AHB_IEP 48 44*4882a593Smuzhiyun #define CLK_AHB_GPU 49 45*4882a593Smuzhiyun #define CLK_APB0_CODEC 50 46*4882a593Smuzhiyun #define CLK_APB0_SPDIF 51 47*4882a593Smuzhiyun #define CLK_APB0_I2S 52 48*4882a593Smuzhiyun #define CLK_APB0_PIO 53 49*4882a593Smuzhiyun #define CLK_APB0_IR 54 50*4882a593Smuzhiyun #define CLK_APB0_KEYPAD 55 51*4882a593Smuzhiyun #define CLK_APB1_I2C0 56 52*4882a593Smuzhiyun #define CLK_APB1_I2C1 57 53*4882a593Smuzhiyun #define CLK_APB1_I2C2 58 54*4882a593Smuzhiyun #define CLK_APB1_UART0 59 55*4882a593Smuzhiyun #define CLK_APB1_UART1 60 56*4882a593Smuzhiyun #define CLK_APB1_UART2 61 57*4882a593Smuzhiyun #define CLK_APB1_UART3 62 58*4882a593Smuzhiyun #define CLK_NAND 63 59*4882a593Smuzhiyun #define CLK_MMC0 64 60*4882a593Smuzhiyun #define CLK_MMC1 65 61*4882a593Smuzhiyun #define CLK_MMC2 66 62*4882a593Smuzhiyun #define CLK_TS 67 63*4882a593Smuzhiyun #define CLK_SS 68 64*4882a593Smuzhiyun #define CLK_SPI0 69 65*4882a593Smuzhiyun #define CLK_SPI1 70 66*4882a593Smuzhiyun #define CLK_SPI2 71 67*4882a593Smuzhiyun #define CLK_IR 72 68*4882a593Smuzhiyun #define CLK_I2S 73 69*4882a593Smuzhiyun #define CLK_SPDIF 74 70*4882a593Smuzhiyun #define CLK_KEYPAD 75 71*4882a593Smuzhiyun #define CLK_USB_OHCI 76 72*4882a593Smuzhiyun #define CLK_USB_PHY0 77 73*4882a593Smuzhiyun #define CLK_USB_PHY1 78 74*4882a593Smuzhiyun #define CLK_GPS 79 75*4882a593Smuzhiyun #define CLK_DRAM_VE 80 76*4882a593Smuzhiyun #define CLK_DRAM_CSI 81 77*4882a593Smuzhiyun #define CLK_DRAM_TS 82 78*4882a593Smuzhiyun #define CLK_DRAM_TVE 83 79*4882a593Smuzhiyun #define CLK_DRAM_DE_FE 84 80*4882a593Smuzhiyun #define CLK_DRAM_DE_BE 85 81*4882a593Smuzhiyun #define CLK_DRAM_ACE 86 82*4882a593Smuzhiyun #define CLK_DRAM_IEP 87 83*4882a593Smuzhiyun #define CLK_DE_BE 88 84*4882a593Smuzhiyun #define CLK_DE_FE 89 85*4882a593Smuzhiyun #define CLK_TCON_CH0 90 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define CLK_TCON_CH1 92 88*4882a593Smuzhiyun #define CLK_CSI 93 89*4882a593Smuzhiyun #define CLK_VE 94 90*4882a593Smuzhiyun #define CLK_CODEC 95 91*4882a593Smuzhiyun #define CLK_AVS 96 92*4882a593Smuzhiyun #define CLK_HDMI 97 93*4882a593Smuzhiyun #define CLK_GPU 98 94*4882a593Smuzhiyun #define CLK_MBUS 99 95*4882a593Smuzhiyun #define CLK_IEP 100 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_SUN5I_H_ */ 98