1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define CLK_AR100 0 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CLK_R_APB1 2 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CLK_R_APB1_TIMER 4 14*4882a593Smuzhiyun #define CLK_R_APB1_TWD 5 15*4882a593Smuzhiyun #define CLK_R_APB1_PWM 6 16*4882a593Smuzhiyun #define CLK_R_APB2_UART 7 17*4882a593Smuzhiyun #define CLK_R_APB2_I2C 8 18*4882a593Smuzhiyun #define CLK_R_APB1_IR 9 19*4882a593Smuzhiyun #define CLK_R_APB1_W1 10 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define CLK_IR 11 22*4882a593Smuzhiyun #define CLK_W1 12 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ 25