1*4882a593Smuzhiyun // SPDX-License-Identifier: (GPL-2.0+ or MIT) 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_ 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_SUN50I_H6_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define CLK_PLL_PERIPH0 3 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CLK_CPUX 21 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CLK_APB1 26 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CLK_DE 29 16*4882a593Smuzhiyun #define CLK_BUS_DE 30 17*4882a593Smuzhiyun #define CLK_DEINTERLACE 31 18*4882a593Smuzhiyun #define CLK_BUS_DEINTERLACE 32 19*4882a593Smuzhiyun #define CLK_GPU 33 20*4882a593Smuzhiyun #define CLK_BUS_GPU 34 21*4882a593Smuzhiyun #define CLK_CE 35 22*4882a593Smuzhiyun #define CLK_BUS_CE 36 23*4882a593Smuzhiyun #define CLK_VE 37 24*4882a593Smuzhiyun #define CLK_BUS_VE 38 25*4882a593Smuzhiyun #define CLK_EMCE 39 26*4882a593Smuzhiyun #define CLK_BUS_EMCE 40 27*4882a593Smuzhiyun #define CLK_VP9 41 28*4882a593Smuzhiyun #define CLK_BUS_VP9 42 29*4882a593Smuzhiyun #define CLK_BUS_DMA 43 30*4882a593Smuzhiyun #define CLK_BUS_MSGBOX 44 31*4882a593Smuzhiyun #define CLK_BUS_SPINLOCK 45 32*4882a593Smuzhiyun #define CLK_BUS_HSTIMER 46 33*4882a593Smuzhiyun #define CLK_AVS 47 34*4882a593Smuzhiyun #define CLK_BUS_DBG 48 35*4882a593Smuzhiyun #define CLK_BUS_PSI 49 36*4882a593Smuzhiyun #define CLK_BUS_PWM 50 37*4882a593Smuzhiyun #define CLK_BUS_IOMMU 51 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define CLK_MBUS_DMA 53 40*4882a593Smuzhiyun #define CLK_MBUS_VE 54 41*4882a593Smuzhiyun #define CLK_MBUS_CE 55 42*4882a593Smuzhiyun #define CLK_MBUS_TS 56 43*4882a593Smuzhiyun #define CLK_MBUS_NAND 57 44*4882a593Smuzhiyun #define CLK_MBUS_CSI 58 45*4882a593Smuzhiyun #define CLK_MBUS_DEINTERLACE 59 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define CLK_NAND0 61 48*4882a593Smuzhiyun #define CLK_NAND1 62 49*4882a593Smuzhiyun #define CLK_BUS_NAND 63 50*4882a593Smuzhiyun #define CLK_MMC0 64 51*4882a593Smuzhiyun #define CLK_MMC1 65 52*4882a593Smuzhiyun #define CLK_MMC2 66 53*4882a593Smuzhiyun #define CLK_BUS_MMC0 67 54*4882a593Smuzhiyun #define CLK_BUS_MMC1 68 55*4882a593Smuzhiyun #define CLK_BUS_MMC2 69 56*4882a593Smuzhiyun #define CLK_BUS_UART0 70 57*4882a593Smuzhiyun #define CLK_BUS_UART1 71 58*4882a593Smuzhiyun #define CLK_BUS_UART2 72 59*4882a593Smuzhiyun #define CLK_BUS_UART3 73 60*4882a593Smuzhiyun #define CLK_BUS_I2C0 74 61*4882a593Smuzhiyun #define CLK_BUS_I2C1 75 62*4882a593Smuzhiyun #define CLK_BUS_I2C2 76 63*4882a593Smuzhiyun #define CLK_BUS_I2C3 77 64*4882a593Smuzhiyun #define CLK_BUS_SCR0 78 65*4882a593Smuzhiyun #define CLK_BUS_SCR1 79 66*4882a593Smuzhiyun #define CLK_SPI0 80 67*4882a593Smuzhiyun #define CLK_SPI1 81 68*4882a593Smuzhiyun #define CLK_BUS_SPI0 82 69*4882a593Smuzhiyun #define CLK_BUS_SPI1 83 70*4882a593Smuzhiyun #define CLK_BUS_EMAC 84 71*4882a593Smuzhiyun #define CLK_TS 85 72*4882a593Smuzhiyun #define CLK_BUS_TS 86 73*4882a593Smuzhiyun #define CLK_IR_TX 87 74*4882a593Smuzhiyun #define CLK_BUS_IR_TX 88 75*4882a593Smuzhiyun #define CLK_BUS_THS 89 76*4882a593Smuzhiyun #define CLK_I2S3 90 77*4882a593Smuzhiyun #define CLK_I2S0 91 78*4882a593Smuzhiyun #define CLK_I2S1 92 79*4882a593Smuzhiyun #define CLK_I2S2 93 80*4882a593Smuzhiyun #define CLK_BUS_I2S0 94 81*4882a593Smuzhiyun #define CLK_BUS_I2S1 95 82*4882a593Smuzhiyun #define CLK_BUS_I2S2 96 83*4882a593Smuzhiyun #define CLK_BUS_I2S3 97 84*4882a593Smuzhiyun #define CLK_SPDIF 98 85*4882a593Smuzhiyun #define CLK_BUS_SPDIF 99 86*4882a593Smuzhiyun #define CLK_DMIC 100 87*4882a593Smuzhiyun #define CLK_BUS_DMIC 101 88*4882a593Smuzhiyun #define CLK_AUDIO_HUB 102 89*4882a593Smuzhiyun #define CLK_BUS_AUDIO_HUB 103 90*4882a593Smuzhiyun #define CLK_USB_OHCI0 104 91*4882a593Smuzhiyun #define CLK_USB_PHY0 105 92*4882a593Smuzhiyun #define CLK_USB_PHY1 106 93*4882a593Smuzhiyun #define CLK_USB_OHCI3 107 94*4882a593Smuzhiyun #define CLK_USB_PHY3 108 95*4882a593Smuzhiyun #define CLK_USB_HSIC_12M 109 96*4882a593Smuzhiyun #define CLK_USB_HSIC 110 97*4882a593Smuzhiyun #define CLK_BUS_OHCI0 111 98*4882a593Smuzhiyun #define CLK_BUS_OHCI3 112 99*4882a593Smuzhiyun #define CLK_BUS_EHCI0 113 100*4882a593Smuzhiyun #define CLK_BUS_XHCI 114 101*4882a593Smuzhiyun #define CLK_BUS_EHCI3 115 102*4882a593Smuzhiyun #define CLK_BUS_OTG 116 103*4882a593Smuzhiyun #define CLK_PCIE_REF_100M 117 104*4882a593Smuzhiyun #define CLK_PCIE_REF 118 105*4882a593Smuzhiyun #define CLK_PCIE_REF_OUT 119 106*4882a593Smuzhiyun #define CLK_PCIE_MAXI 120 107*4882a593Smuzhiyun #define CLK_PCIE_AUX 121 108*4882a593Smuzhiyun #define CLK_BUS_PCIE 122 109*4882a593Smuzhiyun #define CLK_HDMI 123 110*4882a593Smuzhiyun #define CLK_HDMI_SLOW 124 111*4882a593Smuzhiyun #define CLK_HDMI_CEC 125 112*4882a593Smuzhiyun #define CLK_BUS_HDMI 126 113*4882a593Smuzhiyun #define CLK_BUS_TCON_TOP 127 114*4882a593Smuzhiyun #define CLK_TCON_LCD0 128 115*4882a593Smuzhiyun #define CLK_BUS_TCON_LCD0 129 116*4882a593Smuzhiyun #define CLK_TCON_TV0 130 117*4882a593Smuzhiyun #define CLK_BUS_TCON_TV0 131 118*4882a593Smuzhiyun #define CLK_CSI_CCI 132 119*4882a593Smuzhiyun #define CLK_CSI_TOP 133 120*4882a593Smuzhiyun #define CLK_CSI_MCLK 134 121*4882a593Smuzhiyun #define CLK_BUS_CSI 135 122*4882a593Smuzhiyun #define CLK_HDCP 136 123*4882a593Smuzhiyun #define CLK_BUS_HDCP 137 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */ 126