1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define CLK_R_APB1 2 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CLK_R_APB1_TIMER 4 12*4882a593Smuzhiyun #define CLK_R_APB1_TWD 5 13*4882a593Smuzhiyun #define CLK_R_APB1_PWM 6 14*4882a593Smuzhiyun #define CLK_R_APB1_BUS_PWM 7 15*4882a593Smuzhiyun #define CLK_R_APB1_PPU 8 16*4882a593Smuzhiyun #define CLK_R_APB2_UART 9 17*4882a593Smuzhiyun #define CLK_R_APB2_I2C0 10 18*4882a593Smuzhiyun #define CLK_R_APB2_I2C1 11 19*4882a593Smuzhiyun #define CLK_R_APB1_IR 12 20*4882a593Smuzhiyun #define CLK_R_APB1_BUS_IR 13 21*4882a593Smuzhiyun #define CLK_R_AHB_BUS_RTC 14 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ */ 24