1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_SUN50I_A100_H_ 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_SUN50I_A100_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define CLK_PLL_PERIPH0 3 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CLK_CPUX 24 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CLK_APB1 29 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CLK_MBUS 31 16*4882a593Smuzhiyun #define CLK_DE 32 17*4882a593Smuzhiyun #define CLK_BUS_DE 33 18*4882a593Smuzhiyun #define CLK_G2D 34 19*4882a593Smuzhiyun #define CLK_BUS_G2D 35 20*4882a593Smuzhiyun #define CLK_GPU 36 21*4882a593Smuzhiyun #define CLK_BUS_GPU 37 22*4882a593Smuzhiyun #define CLK_CE 38 23*4882a593Smuzhiyun #define CLK_BUS_CE 39 24*4882a593Smuzhiyun #define CLK_VE 40 25*4882a593Smuzhiyun #define CLK_BUS_VE 41 26*4882a593Smuzhiyun #define CLK_BUS_DMA 42 27*4882a593Smuzhiyun #define CLK_BUS_MSGBOX 43 28*4882a593Smuzhiyun #define CLK_BUS_SPINLOCK 44 29*4882a593Smuzhiyun #define CLK_BUS_HSTIMER 45 30*4882a593Smuzhiyun #define CLK_AVS 46 31*4882a593Smuzhiyun #define CLK_BUS_DBG 47 32*4882a593Smuzhiyun #define CLK_BUS_PSI 48 33*4882a593Smuzhiyun #define CLK_BUS_PWM 49 34*4882a593Smuzhiyun #define CLK_BUS_IOMMU 50 35*4882a593Smuzhiyun #define CLK_MBUS_DMA 51 36*4882a593Smuzhiyun #define CLK_MBUS_VE 52 37*4882a593Smuzhiyun #define CLK_MBUS_CE 53 38*4882a593Smuzhiyun #define CLK_MBUS_NAND 54 39*4882a593Smuzhiyun #define CLK_MBUS_CSI 55 40*4882a593Smuzhiyun #define CLK_MBUS_ISP 56 41*4882a593Smuzhiyun #define CLK_MBUS_G2D 57 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define CLK_NAND0 59 44*4882a593Smuzhiyun #define CLK_NAND1 60 45*4882a593Smuzhiyun #define CLK_BUS_NAND 61 46*4882a593Smuzhiyun #define CLK_MMC0 62 47*4882a593Smuzhiyun #define CLK_MMC1 63 48*4882a593Smuzhiyun #define CLK_MMC2 64 49*4882a593Smuzhiyun #define CLK_MMC3 65 50*4882a593Smuzhiyun #define CLK_BUS_MMC0 66 51*4882a593Smuzhiyun #define CLK_BUS_MMC1 67 52*4882a593Smuzhiyun #define CLK_BUS_MMC2 68 53*4882a593Smuzhiyun #define CLK_BUS_UART0 69 54*4882a593Smuzhiyun #define CLK_BUS_UART1 70 55*4882a593Smuzhiyun #define CLK_BUS_UART2 71 56*4882a593Smuzhiyun #define CLK_BUS_UART3 72 57*4882a593Smuzhiyun #define CLK_BUS_UART4 73 58*4882a593Smuzhiyun #define CLK_BUS_I2C0 74 59*4882a593Smuzhiyun #define CLK_BUS_I2C1 75 60*4882a593Smuzhiyun #define CLK_BUS_I2C2 76 61*4882a593Smuzhiyun #define CLK_BUS_I2C3 77 62*4882a593Smuzhiyun #define CLK_SPI0 78 63*4882a593Smuzhiyun #define CLK_SPI1 79 64*4882a593Smuzhiyun #define CLK_SPI2 80 65*4882a593Smuzhiyun #define CLK_BUS_SPI0 81 66*4882a593Smuzhiyun #define CLK_BUS_SPI1 82 67*4882a593Smuzhiyun #define CLK_BUS_SPI2 83 68*4882a593Smuzhiyun #define CLK_EMAC_25M 84 69*4882a593Smuzhiyun #define CLK_BUS_EMAC 85 70*4882a593Smuzhiyun #define CLK_IR_RX 86 71*4882a593Smuzhiyun #define CLK_BUS_IR_RX 87 72*4882a593Smuzhiyun #define CLK_IR_TX 88 73*4882a593Smuzhiyun #define CLK_BUS_IR_TX 89 74*4882a593Smuzhiyun #define CLK_BUS_GPADC 90 75*4882a593Smuzhiyun #define CLK_BUS_THS 91 76*4882a593Smuzhiyun #define CLK_I2S0 92 77*4882a593Smuzhiyun #define CLK_I2S1 93 78*4882a593Smuzhiyun #define CLK_I2S2 94 79*4882a593Smuzhiyun #define CLK_I2S3 95 80*4882a593Smuzhiyun #define CLK_BUS_I2S0 96 81*4882a593Smuzhiyun #define CLK_BUS_I2S1 97 82*4882a593Smuzhiyun #define CLK_BUS_I2S2 98 83*4882a593Smuzhiyun #define CLK_BUS_I2S3 99 84*4882a593Smuzhiyun #define CLK_SPDIF 100 85*4882a593Smuzhiyun #define CLK_BUS_SPDIF 101 86*4882a593Smuzhiyun #define CLK_DMIC 102 87*4882a593Smuzhiyun #define CLK_BUS_DMIC 103 88*4882a593Smuzhiyun #define CLK_AUDIO_DAC 104 89*4882a593Smuzhiyun #define CLK_AUDIO_ADC 105 90*4882a593Smuzhiyun #define CLK_AUDIO_4X 106 91*4882a593Smuzhiyun #define CLK_BUS_AUDIO_CODEC 107 92*4882a593Smuzhiyun #define CLK_USB_OHCI0 108 93*4882a593Smuzhiyun #define CLK_USB_PHY0 109 94*4882a593Smuzhiyun #define CLK_USB_OHCI1 110 95*4882a593Smuzhiyun #define CLK_USB_PHY1 111 96*4882a593Smuzhiyun #define CLK_BUS_OHCI0 112 97*4882a593Smuzhiyun #define CLK_BUS_OHCI1 113 98*4882a593Smuzhiyun #define CLK_BUS_EHCI0 114 99*4882a593Smuzhiyun #define CLK_BUS_EHCI1 115 100*4882a593Smuzhiyun #define CLK_BUS_OTG 116 101*4882a593Smuzhiyun #define CLK_BUS_LRADC 117 102*4882a593Smuzhiyun #define CLK_BUS_DPSS_TOP0 118 103*4882a593Smuzhiyun #define CLK_BUS_DPSS_TOP1 119 104*4882a593Smuzhiyun #define CLK_MIPI_DSI 120 105*4882a593Smuzhiyun #define CLK_BUS_MIPI_DSI 121 106*4882a593Smuzhiyun #define CLK_TCON_LCD 122 107*4882a593Smuzhiyun #define CLK_BUS_TCON_LCD 123 108*4882a593Smuzhiyun #define CLK_LEDC 124 109*4882a593Smuzhiyun #define CLK_BUS_LEDC 125 110*4882a593Smuzhiyun #define CLK_CSI_TOP 126 111*4882a593Smuzhiyun #define CLK_CSI0_MCLK 127 112*4882a593Smuzhiyun #define CLK_CSI1_MCLK 128 113*4882a593Smuzhiyun #define CLK_BUS_CSI 129 114*4882a593Smuzhiyun #define CLK_CSI_ISP 130 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_SUN50I_A100_H_ */ 117