1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2017, Intel Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __STRATIX10_CLOCK_H 7*4882a593Smuzhiyun #define __STRATIX10_CLOCK_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* fixed rate clocks */ 10*4882a593Smuzhiyun #define STRATIX10_OSC1 0 11*4882a593Smuzhiyun #define STRATIX10_CB_INTOSC_HS_DIV2_CLK 1 12*4882a593Smuzhiyun #define STRATIX10_CB_INTOSC_LS_CLK 2 13*4882a593Smuzhiyun #define STRATIX10_F2S_FREE_CLK 3 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* fixed factor clocks */ 16*4882a593Smuzhiyun #define STRATIX10_L4_SYS_FREE_CLK 4 17*4882a593Smuzhiyun #define STRATIX10_MPU_PERIPH_CLK 5 18*4882a593Smuzhiyun #define STRATIX10_MPU_L2RAM_CLK 6 19*4882a593Smuzhiyun #define STRATIX10_SDMMC_CIU_CLK 7 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* PLL clocks */ 22*4882a593Smuzhiyun #define STRATIX10_MAIN_PLL_CLK 8 23*4882a593Smuzhiyun #define STRATIX10_PERIPH_PLL_CLK 9 24*4882a593Smuzhiyun #define STRATIX10_BOOT_CLK 10 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Periph clocks */ 27*4882a593Smuzhiyun #define STRATIX10_MAIN_MPU_BASE_CLK 11 28*4882a593Smuzhiyun #define STRATIX10_MAIN_NOC_BASE_CLK 12 29*4882a593Smuzhiyun #define STRATIX10_MAIN_EMACA_CLK 13 30*4882a593Smuzhiyun #define STRATIX10_MAIN_EMACB_CLK 14 31*4882a593Smuzhiyun #define STRATIX10_MAIN_EMAC_PTP_CLK 15 32*4882a593Smuzhiyun #define STRATIX10_MAIN_GPIO_DB_CLK 16 33*4882a593Smuzhiyun #define STRATIX10_MAIN_SDMMC_CLK 17 34*4882a593Smuzhiyun #define STRATIX10_MAIN_S2F_USR0_CLK 18 35*4882a593Smuzhiyun #define STRATIX10_MAIN_S2F_USR1_CLK 19 36*4882a593Smuzhiyun #define STRATIX10_MAIN_PSI_REF_CLK 20 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define STRATIX10_PERI_MPU_BASE_CLK 21 39*4882a593Smuzhiyun #define STRATIX10_PERI_NOC_BASE_CLK 22 40*4882a593Smuzhiyun #define STRATIX10_PERI_EMACA_CLK 23 41*4882a593Smuzhiyun #define STRATIX10_PERI_EMACB_CLK 24 42*4882a593Smuzhiyun #define STRATIX10_PERI_EMAC_PTP_CLK 25 43*4882a593Smuzhiyun #define STRATIX10_PERI_GPIO_DB_CLK 26 44*4882a593Smuzhiyun #define STRATIX10_PERI_SDMMC_CLK 27 45*4882a593Smuzhiyun #define STRATIX10_PERI_S2F_USR0_CLK 28 46*4882a593Smuzhiyun #define STRATIX10_PERI_S2F_USR1_CLK 29 47*4882a593Smuzhiyun #define STRATIX10_PERI_PSI_REF_CLK 30 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define STRATIX10_MPU_FREE_CLK 31 50*4882a593Smuzhiyun #define STRATIX10_NOC_FREE_CLK 32 51*4882a593Smuzhiyun #define STRATIX10_S2F_USR0_CLK 33 52*4882a593Smuzhiyun #define STRATIX10_NOC_CLK 34 53*4882a593Smuzhiyun #define STRATIX10_EMAC_A_FREE_CLK 35 54*4882a593Smuzhiyun #define STRATIX10_EMAC_B_FREE_CLK 36 55*4882a593Smuzhiyun #define STRATIX10_EMAC_PTP_FREE_CLK 37 56*4882a593Smuzhiyun #define STRATIX10_GPIO_DB_FREE_CLK 38 57*4882a593Smuzhiyun #define STRATIX10_SDMMC_FREE_CLK 39 58*4882a593Smuzhiyun #define STRATIX10_S2F_USER1_FREE_CLK 40 59*4882a593Smuzhiyun #define STRATIX10_PSI_REF_FREE_CLK 41 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Gate clocks */ 62*4882a593Smuzhiyun #define STRATIX10_MPU_CLK 42 63*4882a593Smuzhiyun #define STRATIX10_L4_MAIN_CLK 43 64*4882a593Smuzhiyun #define STRATIX10_L4_MP_CLK 44 65*4882a593Smuzhiyun #define STRATIX10_L4_SP_CLK 45 66*4882a593Smuzhiyun #define STRATIX10_CS_AT_CLK 46 67*4882a593Smuzhiyun #define STRATIX10_CS_TRACE_CLK 47 68*4882a593Smuzhiyun #define STRATIX10_CS_PDBG_CLK 48 69*4882a593Smuzhiyun #define STRATIX10_CS_TIMER_CLK 49 70*4882a593Smuzhiyun #define STRATIX10_S2F_USER0_CLK 50 71*4882a593Smuzhiyun #define STRATIX10_S2F_USER1_CLK 51 72*4882a593Smuzhiyun #define STRATIX10_EMAC0_CLK 52 73*4882a593Smuzhiyun #define STRATIX10_EMAC1_CLK 53 74*4882a593Smuzhiyun #define STRATIX10_EMAC2_CLK 54 75*4882a593Smuzhiyun #define STRATIX10_EMAC_PTP_CLK 55 76*4882a593Smuzhiyun #define STRATIX10_GPIO_DB_CLK 56 77*4882a593Smuzhiyun #define STRATIX10_SDMMC_CLK 57 78*4882a593Smuzhiyun #define STRATIX10_PSI_REF_CLK 58 79*4882a593Smuzhiyun #define STRATIX10_USB_CLK 59 80*4882a593Smuzhiyun #define STRATIX10_SPI_M_CLK 60 81*4882a593Smuzhiyun #define STRATIX10_NAND_CLK 61 82*4882a593Smuzhiyun #define STRATIX10_NAND_X_CLK 62 83*4882a593Smuzhiyun #define STRATIX10_NAND_ECC_CLK 63 84*4882a593Smuzhiyun #define STRATIX10_NUM_CLKS 64 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif /* __STRATIX10_CLOCK_H */ 87