1*4882a593Smuzhiyun /* SYS, CORE AND BUS CLOCKS */ 2*4882a593Smuzhiyun #define SYS_D1CPRE 0 3*4882a593Smuzhiyun #define HCLK 1 4*4882a593Smuzhiyun #define PCLK1 2 5*4882a593Smuzhiyun #define PCLK2 3 6*4882a593Smuzhiyun #define PCLK3 4 7*4882a593Smuzhiyun #define PCLK4 5 8*4882a593Smuzhiyun #define HSI_DIV 6 9*4882a593Smuzhiyun #define HSE_1M 7 10*4882a593Smuzhiyun #define I2S_CKIN 8 11*4882a593Smuzhiyun #define CK_DSI_PHY 9 12*4882a593Smuzhiyun #define HSE_CK 10 13*4882a593Smuzhiyun #define LSE_CK 11 14*4882a593Smuzhiyun #define CSI_KER_DIV122 12 15*4882a593Smuzhiyun #define RTC_CK 13 16*4882a593Smuzhiyun #define CPU_SYSTICK 14 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* OSCILLATOR BANK */ 19*4882a593Smuzhiyun #define OSC_BANK 18 20*4882a593Smuzhiyun #define HSI_CK 18 21*4882a593Smuzhiyun #define HSI_KER_CK 19 22*4882a593Smuzhiyun #define CSI_CK 20 23*4882a593Smuzhiyun #define CSI_KER_CK 21 24*4882a593Smuzhiyun #define RC48_CK 22 25*4882a593Smuzhiyun #define LSI_CK 23 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* MCLOCK BANK */ 28*4882a593Smuzhiyun #define MCLK_BANK 28 29*4882a593Smuzhiyun #define PER_CK 28 30*4882a593Smuzhiyun #define PLLSRC 29 31*4882a593Smuzhiyun #define SYS_CK 30 32*4882a593Smuzhiyun #define TRACEIN_CK 31 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* ODF BANK */ 35*4882a593Smuzhiyun #define ODF_BANK 32 36*4882a593Smuzhiyun #define PLL1_P 32 37*4882a593Smuzhiyun #define PLL1_Q 33 38*4882a593Smuzhiyun #define PLL1_R 34 39*4882a593Smuzhiyun #define PLL2_P 35 40*4882a593Smuzhiyun #define PLL2_Q 36 41*4882a593Smuzhiyun #define PLL2_R 37 42*4882a593Smuzhiyun #define PLL3_P 38 43*4882a593Smuzhiyun #define PLL3_Q 39 44*4882a593Smuzhiyun #define PLL3_R 40 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* MCO BANK */ 47*4882a593Smuzhiyun #define MCO_BANK 41 48*4882a593Smuzhiyun #define MCO1 41 49*4882a593Smuzhiyun #define MCO2 42 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* PERIF BANK */ 52*4882a593Smuzhiyun #define PERIF_BANK 50 53*4882a593Smuzhiyun #define D1SRAM1_CK 50 54*4882a593Smuzhiyun #define ITCM_CK 51 55*4882a593Smuzhiyun #define DTCM2_CK 52 56*4882a593Smuzhiyun #define DTCM1_CK 53 57*4882a593Smuzhiyun #define FLITF_CK 54 58*4882a593Smuzhiyun #define JPGDEC_CK 55 59*4882a593Smuzhiyun #define DMA2D_CK 56 60*4882a593Smuzhiyun #define MDMA_CK 57 61*4882a593Smuzhiyun #define USB2ULPI_CK 58 62*4882a593Smuzhiyun #define USB1ULPI_CK 59 63*4882a593Smuzhiyun #define ETH1RX_CK 60 64*4882a593Smuzhiyun #define ETH1TX_CK 61 65*4882a593Smuzhiyun #define ETH1MAC_CK 62 66*4882a593Smuzhiyun #define ART_CK 63 67*4882a593Smuzhiyun #define DMA2_CK 64 68*4882a593Smuzhiyun #define DMA1_CK 65 69*4882a593Smuzhiyun #define D2SRAM3_CK 66 70*4882a593Smuzhiyun #define D2SRAM2_CK 67 71*4882a593Smuzhiyun #define D2SRAM1_CK 68 72*4882a593Smuzhiyun #define HASH_CK 69 73*4882a593Smuzhiyun #define CRYPT_CK 70 74*4882a593Smuzhiyun #define CAMITF_CK 71 75*4882a593Smuzhiyun #define BKPRAM_CK 72 76*4882a593Smuzhiyun #define HSEM_CK 73 77*4882a593Smuzhiyun #define BDMA_CK 74 78*4882a593Smuzhiyun #define CRC_CK 75 79*4882a593Smuzhiyun #define GPIOK_CK 76 80*4882a593Smuzhiyun #define GPIOJ_CK 77 81*4882a593Smuzhiyun #define GPIOI_CK 78 82*4882a593Smuzhiyun #define GPIOH_CK 79 83*4882a593Smuzhiyun #define GPIOG_CK 80 84*4882a593Smuzhiyun #define GPIOF_CK 81 85*4882a593Smuzhiyun #define GPIOE_CK 82 86*4882a593Smuzhiyun #define GPIOD_CK 83 87*4882a593Smuzhiyun #define GPIOC_CK 84 88*4882a593Smuzhiyun #define GPIOB_CK 85 89*4882a593Smuzhiyun #define GPIOA_CK 86 90*4882a593Smuzhiyun #define WWDG1_CK 87 91*4882a593Smuzhiyun #define DAC12_CK 88 92*4882a593Smuzhiyun #define WWDG2_CK 89 93*4882a593Smuzhiyun #define TIM14_CK 90 94*4882a593Smuzhiyun #define TIM13_CK 91 95*4882a593Smuzhiyun #define TIM12_CK 92 96*4882a593Smuzhiyun #define TIM7_CK 93 97*4882a593Smuzhiyun #define TIM6_CK 94 98*4882a593Smuzhiyun #define TIM5_CK 95 99*4882a593Smuzhiyun #define TIM4_CK 96 100*4882a593Smuzhiyun #define TIM3_CK 97 101*4882a593Smuzhiyun #define TIM2_CK 98 102*4882a593Smuzhiyun #define MDIOS_CK 99 103*4882a593Smuzhiyun #define OPAMP_CK 100 104*4882a593Smuzhiyun #define CRS_CK 101 105*4882a593Smuzhiyun #define TIM17_CK 102 106*4882a593Smuzhiyun #define TIM16_CK 103 107*4882a593Smuzhiyun #define TIM15_CK 104 108*4882a593Smuzhiyun #define TIM8_CK 105 109*4882a593Smuzhiyun #define TIM1_CK 106 110*4882a593Smuzhiyun #define TMPSENS_CK 107 111*4882a593Smuzhiyun #define RTCAPB_CK 108 112*4882a593Smuzhiyun #define VREF_CK 109 113*4882a593Smuzhiyun #define COMP12_CK 110 114*4882a593Smuzhiyun #define SYSCFG_CK 111 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* KERNEL BANK */ 117*4882a593Smuzhiyun #define KERN_BANK 120 118*4882a593Smuzhiyun #define SDMMC1_CK 120 119*4882a593Smuzhiyun #define QUADSPI_CK 121 120*4882a593Smuzhiyun #define FMC_CK 122 121*4882a593Smuzhiyun #define USB2OTG_CK 123 122*4882a593Smuzhiyun #define USB1OTG_CK 124 123*4882a593Smuzhiyun #define ADC12_CK 125 124*4882a593Smuzhiyun #define SDMMC2_CK 126 125*4882a593Smuzhiyun #define RNG_CK 127 126*4882a593Smuzhiyun #define ADC3_CK 128 127*4882a593Smuzhiyun #define DSI_CK 129 128*4882a593Smuzhiyun #define LTDC_CK 130 129*4882a593Smuzhiyun #define USART8_CK 131 130*4882a593Smuzhiyun #define USART7_CK 132 131*4882a593Smuzhiyun #define HDMICEC_CK 133 132*4882a593Smuzhiyun #define I2C3_CK 134 133*4882a593Smuzhiyun #define I2C2_CK 135 134*4882a593Smuzhiyun #define I2C1_CK 136 135*4882a593Smuzhiyun #define UART5_CK 137 136*4882a593Smuzhiyun #define UART4_CK 138 137*4882a593Smuzhiyun #define USART3_CK 139 138*4882a593Smuzhiyun #define USART2_CK 140 139*4882a593Smuzhiyun #define SPDIFRX_CK 141 140*4882a593Smuzhiyun #define SPI3_CK 142 141*4882a593Smuzhiyun #define SPI2_CK 143 142*4882a593Smuzhiyun #define LPTIM1_CK 144 143*4882a593Smuzhiyun #define FDCAN_CK 145 144*4882a593Smuzhiyun #define SWP_CK 146 145*4882a593Smuzhiyun #define HRTIM_CK 147 146*4882a593Smuzhiyun #define DFSDM1_CK 148 147*4882a593Smuzhiyun #define SAI3_CK 149 148*4882a593Smuzhiyun #define SAI2_CK 150 149*4882a593Smuzhiyun #define SAI1_CK 151 150*4882a593Smuzhiyun #define SPI5_CK 152 151*4882a593Smuzhiyun #define SPI4_CK 153 152*4882a593Smuzhiyun #define SPI1_CK 154 153*4882a593Smuzhiyun #define USART6_CK 155 154*4882a593Smuzhiyun #define USART1_CK 156 155*4882a593Smuzhiyun #define SAI4B_CK 157 156*4882a593Smuzhiyun #define SAI4A_CK 158 157*4882a593Smuzhiyun #define LPTIM5_CK 159 158*4882a593Smuzhiyun #define LPTIM4_CK 160 159*4882a593Smuzhiyun #define LPTIM3_CK 161 160*4882a593Smuzhiyun #define LPTIM2_CK 162 161*4882a593Smuzhiyun #define I2C4_CK 163 162*4882a593Smuzhiyun #define SPI6_CK 164 163*4882a593Smuzhiyun #define LPUART1_CK 165 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #define STM32H7_MAX_CLKS 166 166