1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants clk index STMicroelectronics 4*4882a593Smuzhiyun * STiH418 SoC. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_STIH418 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_STIH418 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "stih410-clks.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* STiH418 introduces new clock outputs compared to STiH410 */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* CLOCKGEN C0 */ 14*4882a593Smuzhiyun #define CLK_PROC_BDISP_0 14 15*4882a593Smuzhiyun #define CLK_PROC_BDISP_1 15 16*4882a593Smuzhiyun #define CLK_TX_ICN_1 23 17*4882a593Smuzhiyun #define CLK_ETH_PHYREF 27 18*4882a593Smuzhiyun #define CLK_PP_HEVC 35 19*4882a593Smuzhiyun #define CLK_CLUST_HEVC 36 20*4882a593Smuzhiyun #define CLK_HWPE_HEVC 37 21*4882a593Smuzhiyun #define CLK_FC_HEVC 38 22*4882a593Smuzhiyun #define CLK_PROC_MIXER 39 23*4882a593Smuzhiyun #define CLK_PROC_SC 40 24*4882a593Smuzhiyun #define CLK_AVSP_HEVC 41 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* CLOCKGEN D2 */ 27*4882a593Smuzhiyun #undef CLK_PIX_PIP 28*4882a593Smuzhiyun #undef CLK_PIX_GDP1 29*4882a593Smuzhiyun #undef CLK_PIX_GDP2 30*4882a593Smuzhiyun #undef CLK_PIX_GDP3 31*4882a593Smuzhiyun #undef CLK_PIX_GDP4 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CLK_TMDS_HDMI_DIV2 5 34*4882a593Smuzhiyun #define CLK_VP9 47 35*4882a593Smuzhiyun #endif 36