1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants clk index STMicroelectronics 4*4882a593Smuzhiyun * STiH410 SoC. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_STIH410 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_STIH410 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "stih407-clks.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* STiH410 introduces new clock outputs compared to STiH407 */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* CLOCKGEN C0 */ 14*4882a593Smuzhiyun #define CLK_TX_ICN_HADES 32 15*4882a593Smuzhiyun #define CLK_RX_ICN_HADES 33 16*4882a593Smuzhiyun #define CLK_ICN_REG_16 34 17*4882a593Smuzhiyun #define CLK_PP_HADES 35 18*4882a593Smuzhiyun #define CLK_CLUST_HADES 36 19*4882a593Smuzhiyun #define CLK_HWPE_HADES 37 20*4882a593Smuzhiyun #define CLK_FC_HADES 38 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* CLOCKGEN D0 */ 23*4882a593Smuzhiyun #define CLK_PCMR10_MASTER 4 24*4882a593Smuzhiyun #define CLK_USB2_PHY 5 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #endif 27