1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides constants clk index STMicroelectronics 4*4882a593Smuzhiyun * STiH407 SoC. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_STIH407 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_STIH407 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* CLOCKGEN A0 */ 10*4882a593Smuzhiyun #define CLK_IC_LMI0 0 11*4882a593Smuzhiyun #define CLK_IC_LMI1 1 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* CLOCKGEN C0 */ 14*4882a593Smuzhiyun #define CLK_ICN_GPU 0 15*4882a593Smuzhiyun #define CLK_FDMA 1 16*4882a593Smuzhiyun #define CLK_NAND 2 17*4882a593Smuzhiyun #define CLK_HVA 3 18*4882a593Smuzhiyun #define CLK_PROC_STFE 4 19*4882a593Smuzhiyun #define CLK_PROC_TP 5 20*4882a593Smuzhiyun #define CLK_RX_ICN_DMU 6 21*4882a593Smuzhiyun #define CLK_RX_ICN_DISP_0 6 22*4882a593Smuzhiyun #define CLK_RX_ICN_DISP_1 6 23*4882a593Smuzhiyun #define CLK_RX_ICN_HVA 7 24*4882a593Smuzhiyun #define CLK_RX_ICN_TS 7 25*4882a593Smuzhiyun #define CLK_ICN_CPU 8 26*4882a593Smuzhiyun #define CLK_TX_ICN_DMU 9 27*4882a593Smuzhiyun #define CLK_TX_ICN_HVA 9 28*4882a593Smuzhiyun #define CLK_TX_ICN_TS 9 29*4882a593Smuzhiyun #define CLK_ICN_COMPO 9 30*4882a593Smuzhiyun #define CLK_MMC_0 10 31*4882a593Smuzhiyun #define CLK_MMC_1 11 32*4882a593Smuzhiyun #define CLK_JPEGDEC 12 33*4882a593Smuzhiyun #define CLK_ICN_REG 13 34*4882a593Smuzhiyun #define CLK_TRACE_A9 13 35*4882a593Smuzhiyun #define CLK_PTI_STM 13 36*4882a593Smuzhiyun #define CLK_EXT2F_A9 13 37*4882a593Smuzhiyun #define CLK_IC_BDISP_0 14 38*4882a593Smuzhiyun #define CLK_IC_BDISP_1 15 39*4882a593Smuzhiyun #define CLK_PP_DMU 16 40*4882a593Smuzhiyun #define CLK_VID_DMU 17 41*4882a593Smuzhiyun #define CLK_DSS_LPC 18 42*4882a593Smuzhiyun #define CLK_ST231_AUD_0 19 43*4882a593Smuzhiyun #define CLK_ST231_GP_0 19 44*4882a593Smuzhiyun #define CLK_ST231_GP_1 20 45*4882a593Smuzhiyun #define CLK_ST231_DMU 21 46*4882a593Smuzhiyun #define CLK_ICN_LMI 22 47*4882a593Smuzhiyun #define CLK_TX_ICN_DISP_0 23 48*4882a593Smuzhiyun #define CLK_TX_ICN_DISP_1 23 49*4882a593Smuzhiyun #define CLK_ICN_SBC 24 50*4882a593Smuzhiyun #define CLK_STFE_FRC2 25 51*4882a593Smuzhiyun #define CLK_ETH_PHY 26 52*4882a593Smuzhiyun #define CLK_ETH_REF_PHYCLK 27 53*4882a593Smuzhiyun #define CLK_FLASH_PROMIP 28 54*4882a593Smuzhiyun #define CLK_MAIN_DISP 29 55*4882a593Smuzhiyun #define CLK_AUX_DISP 30 56*4882a593Smuzhiyun #define CLK_COMPO_DVP 31 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* CLOCKGEN D0 */ 59*4882a593Smuzhiyun #define CLK_PCM_0 0 60*4882a593Smuzhiyun #define CLK_PCM_1 1 61*4882a593Smuzhiyun #define CLK_PCM_2 2 62*4882a593Smuzhiyun #define CLK_SPDIFF 3 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* CLOCKGEN D2 */ 65*4882a593Smuzhiyun #define CLK_PIX_MAIN_DISP 0 66*4882a593Smuzhiyun #define CLK_PIX_PIP 1 67*4882a593Smuzhiyun #define CLK_PIX_GDP1 2 68*4882a593Smuzhiyun #define CLK_PIX_GDP2 3 69*4882a593Smuzhiyun #define CLK_PIX_GDP3 4 70*4882a593Smuzhiyun #define CLK_PIX_GDP4 5 71*4882a593Smuzhiyun #define CLK_PIX_AUX_DISP 6 72*4882a593Smuzhiyun #define CLK_DENC 7 73*4882a593Smuzhiyun #define CLK_PIX_HDDAC 8 74*4882a593Smuzhiyun #define CLK_HDDAC 9 75*4882a593Smuzhiyun #define CLK_SDDAC 10 76*4882a593Smuzhiyun #define CLK_PIX_DVO 11 77*4882a593Smuzhiyun #define CLK_DVO 12 78*4882a593Smuzhiyun #define CLK_PIX_HDMI 13 79*4882a593Smuzhiyun #define CLK_TMDS_HDMI 14 80*4882a593Smuzhiyun #define CLK_REF_HDMIPHY 15 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* CLOCKGEN D3 */ 83*4882a593Smuzhiyun #define CLK_STFE_FRC1 0 84*4882a593Smuzhiyun #define CLK_TSOUT_0 1 85*4882a593Smuzhiyun #define CLK_TSOUT_1 2 86*4882a593Smuzhiyun #define CLK_MCHI 3 87*4882a593Smuzhiyun #define CLK_VSENS_COMPO 4 88*4882a593Smuzhiyun #define CLK_FRC1_REMOTE 5 89*4882a593Smuzhiyun #define CLK_LPC_0 6 90*4882a593Smuzhiyun #define CLK_LPC_1 7 91*4882a593Smuzhiyun #endif 92