1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2018-2019 SiFive, Inc. 4*4882a593Smuzhiyun * Wesley Terpstra 5*4882a593Smuzhiyun * Paul Walmsley 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H 9*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Clock indexes for use by Device Tree data and the PRCI driver */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define PRCI_CLK_COREPLL 0 14*4882a593Smuzhiyun #define PRCI_CLK_DDRPLL 1 15*4882a593Smuzhiyun #define PRCI_CLK_GEMGXLPLL 2 16*4882a593Smuzhiyun #define PRCI_CLK_TLCLK 3 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #endif 19