1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2014 Ulrich Hecht 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_SH73A0_H__ 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_SH73A0_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* CPG */ 10*4882a593Smuzhiyun #define SH73A0_CLK_MAIN 0 11*4882a593Smuzhiyun #define SH73A0_CLK_PLL0 1 12*4882a593Smuzhiyun #define SH73A0_CLK_PLL1 2 13*4882a593Smuzhiyun #define SH73A0_CLK_PLL2 3 14*4882a593Smuzhiyun #define SH73A0_CLK_PLL3 4 15*4882a593Smuzhiyun #define SH73A0_CLK_DSI0PHY 5 16*4882a593Smuzhiyun #define SH73A0_CLK_DSI1PHY 6 17*4882a593Smuzhiyun #define SH73A0_CLK_ZG 7 18*4882a593Smuzhiyun #define SH73A0_CLK_M3 8 19*4882a593Smuzhiyun #define SH73A0_CLK_B 9 20*4882a593Smuzhiyun #define SH73A0_CLK_M1 10 21*4882a593Smuzhiyun #define SH73A0_CLK_M2 11 22*4882a593Smuzhiyun #define SH73A0_CLK_Z 12 23*4882a593Smuzhiyun #define SH73A0_CLK_ZX 13 24*4882a593Smuzhiyun #define SH73A0_CLK_HP 14 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* MSTP0 */ 27*4882a593Smuzhiyun #define SH73A0_CLK_IIC2 1 28*4882a593Smuzhiyun #define SH73A0_CLK_MSIOF0 0 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* MSTP1 */ 31*4882a593Smuzhiyun #define SH73A0_CLK_CEU1 29 32*4882a593Smuzhiyun #define SH73A0_CLK_CSI2_RX1 28 33*4882a593Smuzhiyun #define SH73A0_CLK_CEU0 27 34*4882a593Smuzhiyun #define SH73A0_CLK_CSI2_RX0 26 35*4882a593Smuzhiyun #define SH73A0_CLK_TMU0 25 36*4882a593Smuzhiyun #define SH73A0_CLK_DSITX0 18 37*4882a593Smuzhiyun #define SH73A0_CLK_IIC0 16 38*4882a593Smuzhiyun #define SH73A0_CLK_SGX 12 39*4882a593Smuzhiyun #define SH73A0_CLK_LCDC0 0 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* MSTP2 */ 42*4882a593Smuzhiyun #define SH73A0_CLK_SCIFA7 19 43*4882a593Smuzhiyun #define SH73A0_CLK_SY_DMAC 18 44*4882a593Smuzhiyun #define SH73A0_CLK_MP_DMAC 17 45*4882a593Smuzhiyun #define SH73A0_CLK_MSIOF3 15 46*4882a593Smuzhiyun #define SH73A0_CLK_MSIOF1 8 47*4882a593Smuzhiyun #define SH73A0_CLK_SCIFA5 7 48*4882a593Smuzhiyun #define SH73A0_CLK_SCIFB 6 49*4882a593Smuzhiyun #define SH73A0_CLK_MSIOF2 5 50*4882a593Smuzhiyun #define SH73A0_CLK_SCIFA0 4 51*4882a593Smuzhiyun #define SH73A0_CLK_SCIFA1 3 52*4882a593Smuzhiyun #define SH73A0_CLK_SCIFA2 2 53*4882a593Smuzhiyun #define SH73A0_CLK_SCIFA3 1 54*4882a593Smuzhiyun #define SH73A0_CLK_SCIFA4 0 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* MSTP3 */ 57*4882a593Smuzhiyun #define SH73A0_CLK_SCIFA6 31 58*4882a593Smuzhiyun #define SH73A0_CLK_CMT1 29 59*4882a593Smuzhiyun #define SH73A0_CLK_FSI 28 60*4882a593Smuzhiyun #define SH73A0_CLK_IRDA 25 61*4882a593Smuzhiyun #define SH73A0_CLK_IIC1 23 62*4882a593Smuzhiyun #define SH73A0_CLK_USB 22 63*4882a593Smuzhiyun #define SH73A0_CLK_FLCTL 15 64*4882a593Smuzhiyun #define SH73A0_CLK_SDHI0 14 65*4882a593Smuzhiyun #define SH73A0_CLK_SDHI1 13 66*4882a593Smuzhiyun #define SH73A0_CLK_MMCIF0 12 67*4882a593Smuzhiyun #define SH73A0_CLK_SDHI2 11 68*4882a593Smuzhiyun #define SH73A0_CLK_TPU0 4 69*4882a593Smuzhiyun #define SH73A0_CLK_TPU1 3 70*4882a593Smuzhiyun #define SH73A0_CLK_TPU2 2 71*4882a593Smuzhiyun #define SH73A0_CLK_TPU3 1 72*4882a593Smuzhiyun #define SH73A0_CLK_TPU4 0 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* MSTP4 */ 75*4882a593Smuzhiyun #define SH73A0_CLK_IIC3 11 76*4882a593Smuzhiyun #define SH73A0_CLK_IIC4 10 77*4882a593Smuzhiyun #define SH73A0_CLK_KEYSC 3 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* MSTP5 */ 80*4882a593Smuzhiyun #define SH73A0_CLK_INTCA0 8 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #endif 83