1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 Tomasz Figa <tomasz.figa@gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This header provides constants for Samsung audio subsystem 6*4882a593Smuzhiyun * clock controller. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * The constants defined in this header are being used in dts 9*4882a593Smuzhiyun * and s5pv210 audss driver. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H 13*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CLK_MOUT_AUDSS 0 16*4882a593Smuzhiyun #define CLK_MOUT_I2S_A 1 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CLK_DOUT_AUD_BUS 2 19*4882a593Smuzhiyun #define CLK_DOUT_I2S_A 3 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define CLK_I2S 4 22*4882a593Smuzhiyun #define CLK_HCLK_I2S 5 23*4882a593Smuzhiyun #define CLK_HCLK_UART 6 24*4882a593Smuzhiyun #define CLK_HCLK_HWA 7 25*4882a593Smuzhiyun #define CLK_HCLK_DMA 8 26*4882a593Smuzhiyun #define CLK_HCLK_BUF 9 27*4882a593Smuzhiyun #define CLK_HCLK_RP 10 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define AUDSS_MAX_CLKS 11 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #endif 32