1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 Rockchip Electronics Co. Ltd. 4*4882a593Smuzhiyun * Author: Finley Xiao <finley.xiao@rock-chips.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* pmucru-clocks indices */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* pll clocks */ 13*4882a593Smuzhiyun #define PLL_GPLL 1 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* sclk (special clocks) */ 16*4882a593Smuzhiyun #define CLK_OSC0_DIV32K 2 17*4882a593Smuzhiyun #define CLK_RTC32K 3 18*4882a593Smuzhiyun #define CLK_WIFI_DIV 4 19*4882a593Smuzhiyun #define CLK_WIFI_OSC0 5 20*4882a593Smuzhiyun #define CLK_WIFI 6 21*4882a593Smuzhiyun #define CLK_PMU 7 22*4882a593Smuzhiyun #define SCLK_UART1_DIV 8 23*4882a593Smuzhiyun #define SCLK_UART1_FRACDIV 9 24*4882a593Smuzhiyun #define SCLK_UART1_MUX 10 25*4882a593Smuzhiyun #define SCLK_UART1 11 26*4882a593Smuzhiyun #define CLK_I2C0 12 27*4882a593Smuzhiyun #define CLK_I2C2 13 28*4882a593Smuzhiyun #define CLK_CAPTURE_PWM0 14 29*4882a593Smuzhiyun #define CLK_PWM0 15 30*4882a593Smuzhiyun #define CLK_CAPTURE_PWM1 16 31*4882a593Smuzhiyun #define CLK_PWM1 17 32*4882a593Smuzhiyun #define CLK_SPI0 18 33*4882a593Smuzhiyun #define DBCLK_GPIO0 19 34*4882a593Smuzhiyun #define CLK_PMUPVTM 20 35*4882a593Smuzhiyun #define CLK_CORE_PMUPVTM 21 36*4882a593Smuzhiyun #define CLK_REF12M 22 37*4882a593Smuzhiyun #define CLK_USBPHY_OTG_REF 23 38*4882a593Smuzhiyun #define CLK_USBPHY_HOST_REF 24 39*4882a593Smuzhiyun #define CLK_REF24M 25 40*4882a593Smuzhiyun #define CLK_MIPIDSIPHY_REF 26 41*4882a593Smuzhiyun #define CLK_32K_IOE 27 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* pclk */ 44*4882a593Smuzhiyun #define PCLK_PDPMU 30 45*4882a593Smuzhiyun #define PCLK_PMU 31 46*4882a593Smuzhiyun #define PCLK_UART1 32 47*4882a593Smuzhiyun #define PCLK_I2C0 33 48*4882a593Smuzhiyun #define PCLK_I2C2 34 49*4882a593Smuzhiyun #define PCLK_PWM0 35 50*4882a593Smuzhiyun #define PCLK_PWM1 36 51*4882a593Smuzhiyun #define PCLK_SPI0 37 52*4882a593Smuzhiyun #define PCLK_GPIO0 38 53*4882a593Smuzhiyun #define PCLK_PMUSGRF 39 54*4882a593Smuzhiyun #define PCLK_PMUGRF 40 55*4882a593Smuzhiyun #define PCLK_PMUCRU 41 56*4882a593Smuzhiyun #define PCLK_CHIPVEROTP 42 57*4882a593Smuzhiyun #define PCLK_PDPMU_NIU 43 58*4882a593Smuzhiyun #define PCLK_PMUPVTM 44 59*4882a593Smuzhiyun #define PCLK_SCRKEYGEN 45 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* cru-clocks indices */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* pll clocks */ 66*4882a593Smuzhiyun #define PLL_APLL 1 67*4882a593Smuzhiyun #define PLL_DPLL 2 68*4882a593Smuzhiyun #define PLL_CPLL 3 69*4882a593Smuzhiyun #define PLL_HPLL 4 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* sclk (special clocks) */ 72*4882a593Smuzhiyun #define ARMCLK 5 73*4882a593Smuzhiyun #define USB480M 6 74*4882a593Smuzhiyun #define CLK_CORE_CPUPVTM 7 75*4882a593Smuzhiyun #define CLK_CPUPVTM 8 76*4882a593Smuzhiyun #define CLK_SCR1 9 77*4882a593Smuzhiyun #define CLK_SCR1_CORE 10 78*4882a593Smuzhiyun #define CLK_SCR1_RTC 11 79*4882a593Smuzhiyun #define CLK_SCR1_JTAG 12 80*4882a593Smuzhiyun #define SCLK_UART0_DIV 13 81*4882a593Smuzhiyun #define SCLK_UART0_FRAC 14 82*4882a593Smuzhiyun #define SCLK_UART0_MUX 15 83*4882a593Smuzhiyun #define SCLK_UART0 16 84*4882a593Smuzhiyun #define SCLK_UART2_DIV 17 85*4882a593Smuzhiyun #define SCLK_UART2_FRAC 18 86*4882a593Smuzhiyun #define SCLK_UART2_MUX 19 87*4882a593Smuzhiyun #define SCLK_UART2 20 88*4882a593Smuzhiyun #define SCLK_UART3_DIV 21 89*4882a593Smuzhiyun #define SCLK_UART3_FRAC 22 90*4882a593Smuzhiyun #define SCLK_UART3_MUX 23 91*4882a593Smuzhiyun #define SCLK_UART3 24 92*4882a593Smuzhiyun #define SCLK_UART4_DIV 25 93*4882a593Smuzhiyun #define SCLK_UART4_FRAC 26 94*4882a593Smuzhiyun #define SCLK_UART4_MUX 27 95*4882a593Smuzhiyun #define SCLK_UART4 28 96*4882a593Smuzhiyun #define SCLK_UART5_DIV 29 97*4882a593Smuzhiyun #define SCLK_UART5_FRAC 30 98*4882a593Smuzhiyun #define SCLK_UART5_MUX 31 99*4882a593Smuzhiyun #define SCLK_UART5 32 100*4882a593Smuzhiyun #define CLK_I2C1 33 101*4882a593Smuzhiyun #define CLK_I2C3 34 102*4882a593Smuzhiyun #define CLK_I2C4 35 103*4882a593Smuzhiyun #define CLK_I2C5 36 104*4882a593Smuzhiyun #define CLK_SPI1 37 105*4882a593Smuzhiyun #define CLK_CAPTURE_PWM2 38 106*4882a593Smuzhiyun #define CLK_PWM2 39 107*4882a593Smuzhiyun #define DBCLK_GPIO1 40 108*4882a593Smuzhiyun #define DBCLK_GPIO2 41 109*4882a593Smuzhiyun #define DBCLK_GPIO3 42 110*4882a593Smuzhiyun #define DBCLK_GPIO4 43 111*4882a593Smuzhiyun #define CLK_SARADC 44 112*4882a593Smuzhiyun #define CLK_TIMER0 45 113*4882a593Smuzhiyun #define CLK_TIMER1 46 114*4882a593Smuzhiyun #define CLK_TIMER2 47 115*4882a593Smuzhiyun #define CLK_TIMER3 48 116*4882a593Smuzhiyun #define CLK_TIMER4 49 117*4882a593Smuzhiyun #define CLK_TIMER5 50 118*4882a593Smuzhiyun #define CLK_CAN 51 119*4882a593Smuzhiyun #define CLK_NPU_TSADC 52 120*4882a593Smuzhiyun #define CLK_NPU_TSADCPHY 53 121*4882a593Smuzhiyun #define CLK_CPU_TSADC 54 122*4882a593Smuzhiyun #define CLK_CPU_TSADCPHY 55 123*4882a593Smuzhiyun #define CLK_CRYPTO_CORE 56 124*4882a593Smuzhiyun #define CLK_CRYPTO_PKA 57 125*4882a593Smuzhiyun #define MCLK_I2S0_TX_DIV 58 126*4882a593Smuzhiyun #define MCLK_I2S0_TX_FRACDIV 59 127*4882a593Smuzhiyun #define MCLK_I2S0_TX_MUX 60 128*4882a593Smuzhiyun #define MCLK_I2S0_TX 61 129*4882a593Smuzhiyun #define MCLK_I2S0_RX_DIV 62 130*4882a593Smuzhiyun #define MCLK_I2S0_RX_FRACDIV 63 131*4882a593Smuzhiyun #define MCLK_I2S0_RX_MUX 64 132*4882a593Smuzhiyun #define MCLK_I2S0_RX 65 133*4882a593Smuzhiyun #define MCLK_I2S0_TX_OUT2IO 66 134*4882a593Smuzhiyun #define MCLK_I2S0_RX_OUT2IO 67 135*4882a593Smuzhiyun #define MCLK_I2S1_DIV 68 136*4882a593Smuzhiyun #define MCLK_I2S1_FRACDIV 69 137*4882a593Smuzhiyun #define MCLK_I2S1_MUX 70 138*4882a593Smuzhiyun #define MCLK_I2S1 71 139*4882a593Smuzhiyun #define MCLK_I2S1_OUT2IO 72 140*4882a593Smuzhiyun #define MCLK_I2S2_DIV 73 141*4882a593Smuzhiyun #define MCLK_I2S2_FRACDIV 74 142*4882a593Smuzhiyun #define MCLK_I2S2_MUX 75 143*4882a593Smuzhiyun #define MCLK_I2S2 76 144*4882a593Smuzhiyun #define MCLK_I2S2_OUT2IO 77 145*4882a593Smuzhiyun #define MCLK_PDM 78 146*4882a593Smuzhiyun #define SCLK_ADUPWM_DIV 79 147*4882a593Smuzhiyun #define SCLK_AUDPWM_FRACDIV 80 148*4882a593Smuzhiyun #define SCLK_AUDPWM_MUX 81 149*4882a593Smuzhiyun #define SCLK_AUDPWM 82 150*4882a593Smuzhiyun #define CLK_ACDCDIG_ADC 83 151*4882a593Smuzhiyun #define CLK_ACDCDIG_DAC 84 152*4882a593Smuzhiyun #define CLK_ACDCDIG_I2C 85 153*4882a593Smuzhiyun #define CLK_VENC_CORE 86 154*4882a593Smuzhiyun #define CLK_VDEC_CORE 87 155*4882a593Smuzhiyun #define CLK_VDEC_CA 88 156*4882a593Smuzhiyun #define CLK_VDEC_HEVC_CA 89 157*4882a593Smuzhiyun #define CLK_RGA_CORE 90 158*4882a593Smuzhiyun #define CLK_IEP_CORE 91 159*4882a593Smuzhiyun #define CLK_ISP_DIV 92 160*4882a593Smuzhiyun #define CLK_ISP_NP5 93 161*4882a593Smuzhiyun #define CLK_ISP_NUX 94 162*4882a593Smuzhiyun #define CLK_ISP 95 163*4882a593Smuzhiyun #define CLK_CIF_OUT_DIV 96 164*4882a593Smuzhiyun #define CLK_CIF_OUT_FRACDIV 97 165*4882a593Smuzhiyun #define CLK_CIF_OUT_MUX 98 166*4882a593Smuzhiyun #define CLK_CIF_OUT 99 167*4882a593Smuzhiyun #define CLK_MIPICSI_OUT_DIV 100 168*4882a593Smuzhiyun #define CLK_MIPICSI_OUT_FRACDIV 101 169*4882a593Smuzhiyun #define CLK_MIPICSI_OUT_MUX 102 170*4882a593Smuzhiyun #define CLK_MIPICSI_OUT 103 171*4882a593Smuzhiyun #define CLK_ISPP_DIV 104 172*4882a593Smuzhiyun #define CLK_ISPP_NP5 105 173*4882a593Smuzhiyun #define CLK_ISPP_NUX 106 174*4882a593Smuzhiyun #define CLK_ISPP 107 175*4882a593Smuzhiyun #define CLK_SDMMC 108 176*4882a593Smuzhiyun #define SCLK_SDMMC_DRV 109 177*4882a593Smuzhiyun #define SCLK_SDMMC_SAMPLE 110 178*4882a593Smuzhiyun #define CLK_SDIO 111 179*4882a593Smuzhiyun #define SCLK_SDIO_DRV 112 180*4882a593Smuzhiyun #define SCLK_SDIO_SAMPLE 113 181*4882a593Smuzhiyun #define CLK_EMMC 114 182*4882a593Smuzhiyun #define SCLK_EMMC_DRV 115 183*4882a593Smuzhiyun #define SCLK_EMMC_SAMPLE 116 184*4882a593Smuzhiyun #define CLK_NANDC 117 185*4882a593Smuzhiyun #define SCLK_SFC 118 186*4882a593Smuzhiyun #define CLK_USBHOST_UTMI_OHCI 119 187*4882a593Smuzhiyun #define CLK_USBOTG_REF 120 188*4882a593Smuzhiyun #define CLK_GMAC_DIV 121 189*4882a593Smuzhiyun #define CLK_GMAC_RGMII_M0 122 190*4882a593Smuzhiyun #define CLK_GMAC_SRC_M0 123 191*4882a593Smuzhiyun #define CLK_GMAC_RGMII_M1 124 192*4882a593Smuzhiyun #define CLK_GMAC_SRC_M1 125 193*4882a593Smuzhiyun #define CLK_GMAC_SRC 126 194*4882a593Smuzhiyun #define CLK_GMAC_REF 127 195*4882a593Smuzhiyun #define CLK_GMAC_TX_SRC 128 196*4882a593Smuzhiyun #define CLK_GMAC_TX_DIV5 129 197*4882a593Smuzhiyun #define CLK_GMAC_TX_DIV50 130 198*4882a593Smuzhiyun #define RGMII_MODE_CLK 131 199*4882a593Smuzhiyun #define CLK_GMAC_RX_SRC 132 200*4882a593Smuzhiyun #define CLK_GMAC_RX_DIV2 133 201*4882a593Smuzhiyun #define CLK_GMAC_RX_DIV20 134 202*4882a593Smuzhiyun #define RMII_MODE_CLK 135 203*4882a593Smuzhiyun #define CLK_GMAC_TX_RX 136 204*4882a593Smuzhiyun #define CLK_GMAC_PTPREF 137 205*4882a593Smuzhiyun #define CLK_GMAC_ETHERNET_OUT 138 206*4882a593Smuzhiyun #define CLK_DDRPHY 139 207*4882a593Smuzhiyun #define CLK_DDR_MON 140 208*4882a593Smuzhiyun #define TMCLK_DDR_MON 141 209*4882a593Smuzhiyun #define CLK_NPU_DIV 142 210*4882a593Smuzhiyun #define CLK_NPU_NP5 143 211*4882a593Smuzhiyun #define CLK_CORE_NPU 144 212*4882a593Smuzhiyun #define CLK_CORE_NPUPVTM 145 213*4882a593Smuzhiyun #define CLK_NPUPVTM 146 214*4882a593Smuzhiyun #define SCLK_DDRCLK 147 215*4882a593Smuzhiyun #define CLK_OTP 148 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /* dclk */ 218*4882a593Smuzhiyun #define DCLK_DECOM 150 219*4882a593Smuzhiyun #define DCLK_VOP_DIV 151 220*4882a593Smuzhiyun #define DCLK_VOP_FRACDIV 152 221*4882a593Smuzhiyun #define DCLK_VOP_MUX 153 222*4882a593Smuzhiyun #define DCLK_VOP 154 223*4882a593Smuzhiyun #define DCLK_CIF 155 224*4882a593Smuzhiyun #define DCLK_CIFLITE 156 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun /* aclk */ 227*4882a593Smuzhiyun #define ACLK_PDBUS 160 228*4882a593Smuzhiyun #define ACLK_DMAC 161 229*4882a593Smuzhiyun #define ACLK_DCF 162 230*4882a593Smuzhiyun #define ACLK_SPINLOCK 163 231*4882a593Smuzhiyun #define ACLK_DECOM 164 232*4882a593Smuzhiyun #define ACLK_PDCRYPTO 165 233*4882a593Smuzhiyun #define ACLK_CRYPTO 166 234*4882a593Smuzhiyun #define ACLK_PDVEPU 167 235*4882a593Smuzhiyun #define ACLK_VENC 168 236*4882a593Smuzhiyun #define ACLK_PDVDEC 169 237*4882a593Smuzhiyun #define ACLK_PDJPEG 170 238*4882a593Smuzhiyun #define ACLK_VDEC 171 239*4882a593Smuzhiyun #define ACLK_JPEG 172 240*4882a593Smuzhiyun #define ACLK_PDVO 173 241*4882a593Smuzhiyun #define ACLK_RGA 174 242*4882a593Smuzhiyun #define ACLK_VOP 175 243*4882a593Smuzhiyun #define ACLK_IEP 176 244*4882a593Smuzhiyun #define ACLK_PDVI_DIV 177 245*4882a593Smuzhiyun #define ACLK_PDVI_NP5 178 246*4882a593Smuzhiyun #define ACLK_PDVI 179 247*4882a593Smuzhiyun #define ACLK_ISP 180 248*4882a593Smuzhiyun #define ACLK_CIF 181 249*4882a593Smuzhiyun #define ACLK_CIFLITE 182 250*4882a593Smuzhiyun #define ACLK_PDISPP_DIV 183 251*4882a593Smuzhiyun #define ACLK_PDISPP_NP5 184 252*4882a593Smuzhiyun #define ACLK_PDISPP 185 253*4882a593Smuzhiyun #define ACLK_ISPP 186 254*4882a593Smuzhiyun #define ACLK_PDPHP 187 255*4882a593Smuzhiyun #define ACLK_PDUSB 188 256*4882a593Smuzhiyun #define ACLK_USBOTG 189 257*4882a593Smuzhiyun #define ACLK_PDGMAC 190 258*4882a593Smuzhiyun #define ACLK_GMAC 191 259*4882a593Smuzhiyun #define ACLK_PDNPU_DIV 192 260*4882a593Smuzhiyun #define ACLK_PDNPU_NP5 193 261*4882a593Smuzhiyun #define ACLK_PDNPU 194 262*4882a593Smuzhiyun #define ACLK_NPU 195 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun /* hclk */ 265*4882a593Smuzhiyun #define HCLK_PDCORE_NIU 200 266*4882a593Smuzhiyun #define HCLK_PDUSB 201 267*4882a593Smuzhiyun #define HCLK_PDCRYPTO 202 268*4882a593Smuzhiyun #define HCLK_CRYPTO 203 269*4882a593Smuzhiyun #define HCLK_PDAUDIO 204 270*4882a593Smuzhiyun #define HCLK_I2S0 205 271*4882a593Smuzhiyun #define HCLK_I2S1 206 272*4882a593Smuzhiyun #define HCLK_I2S2 207 273*4882a593Smuzhiyun #define HCLK_PDM 208 274*4882a593Smuzhiyun #define HCLK_AUDPWM 209 275*4882a593Smuzhiyun #define HCLK_PDVEPU 210 276*4882a593Smuzhiyun #define HCLK_VENC 211 277*4882a593Smuzhiyun #define HCLK_PDVDEC 212 278*4882a593Smuzhiyun #define HCLK_PDJPEG 213 279*4882a593Smuzhiyun #define HCLK_VDEC 214 280*4882a593Smuzhiyun #define HCLK_JPEG 215 281*4882a593Smuzhiyun #define HCLK_PDVO 216 282*4882a593Smuzhiyun #define HCLK_RGA 217 283*4882a593Smuzhiyun #define HCLK_VOP 218 284*4882a593Smuzhiyun #define HCLK_IEP 219 285*4882a593Smuzhiyun #define HCLK_PDVI 220 286*4882a593Smuzhiyun #define HCLK_ISP 221 287*4882a593Smuzhiyun #define HCLK_CIF 222 288*4882a593Smuzhiyun #define HCLK_CIFLITE 223 289*4882a593Smuzhiyun #define HCLK_PDISPP 224 290*4882a593Smuzhiyun #define HCLK_ISPP 225 291*4882a593Smuzhiyun #define HCLK_PDPHP 226 292*4882a593Smuzhiyun #define HCLK_PDSDMMC 227 293*4882a593Smuzhiyun #define HCLK_SDMMC 228 294*4882a593Smuzhiyun #define HCLK_PDSDIO 229 295*4882a593Smuzhiyun #define HCLK_SDIO 230 296*4882a593Smuzhiyun #define HCLK_PDNVM 231 297*4882a593Smuzhiyun #define HCLK_EMMC 232 298*4882a593Smuzhiyun #define HCLK_NANDC 233 299*4882a593Smuzhiyun #define HCLK_SFC 234 300*4882a593Smuzhiyun #define HCLK_SFCXIP 235 301*4882a593Smuzhiyun #define HCLK_PDBUS 236 302*4882a593Smuzhiyun #define HCLK_USBHOST 237 303*4882a593Smuzhiyun #define HCLK_USBHOST_ARB 238 304*4882a593Smuzhiyun #define HCLK_PDNPU 239 305*4882a593Smuzhiyun #define HCLK_NPU 240 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /* pclk */ 308*4882a593Smuzhiyun #define PCLK_CPUPVTM 245 309*4882a593Smuzhiyun #define PCLK_PDBUS 246 310*4882a593Smuzhiyun #define PCLK_DCF 247 311*4882a593Smuzhiyun #define PCLK_WDT 248 312*4882a593Smuzhiyun #define PCLK_MAILBOX 249 313*4882a593Smuzhiyun #define PCLK_UART0 250 314*4882a593Smuzhiyun #define PCLK_UART2 251 315*4882a593Smuzhiyun #define PCLK_UART3 252 316*4882a593Smuzhiyun #define PCLK_UART4 253 317*4882a593Smuzhiyun #define PCLK_UART5 254 318*4882a593Smuzhiyun #define PCLK_I2C1 255 319*4882a593Smuzhiyun #define PCLK_I2C3 256 320*4882a593Smuzhiyun #define PCLK_I2C4 257 321*4882a593Smuzhiyun #define PCLK_I2C5 258 322*4882a593Smuzhiyun #define PCLK_SPI1 259 323*4882a593Smuzhiyun #define PCLK_PWM2 261 324*4882a593Smuzhiyun #define PCLK_GPIO1 262 325*4882a593Smuzhiyun #define PCLK_GPIO2 263 326*4882a593Smuzhiyun #define PCLK_GPIO3 264 327*4882a593Smuzhiyun #define PCLK_GPIO4 265 328*4882a593Smuzhiyun #define PCLK_SARADC 266 329*4882a593Smuzhiyun #define PCLK_TIMER 267 330*4882a593Smuzhiyun #define PCLK_DECOM 268 331*4882a593Smuzhiyun #define PCLK_CAN 269 332*4882a593Smuzhiyun #define PCLK_NPU_TSADC 270 333*4882a593Smuzhiyun #define PCLK_CPU_TSADC 271 334*4882a593Smuzhiyun #define PCLK_ACDCDIG 272 335*4882a593Smuzhiyun #define PCLK_PDVO 273 336*4882a593Smuzhiyun #define PCLK_DSIHOST 274 337*4882a593Smuzhiyun #define PCLK_PDVI 275 338*4882a593Smuzhiyun #define PCLK_CSIHOST 276 339*4882a593Smuzhiyun #define PCLK_PDGMAC 277 340*4882a593Smuzhiyun #define PCLK_GMAC 278 341*4882a593Smuzhiyun #define PCLK_PDDDR 279 342*4882a593Smuzhiyun #define PCLK_DDR_MON 280 343*4882a593Smuzhiyun #define PCLK_PDNPU 281 344*4882a593Smuzhiyun #define PCLK_NPUPVTM 282 345*4882a593Smuzhiyun #define PCLK_PDTOP 283 346*4882a593Smuzhiyun #define PCLK_TOPCRU 284 347*4882a593Smuzhiyun #define PCLK_TOPGRF 285 348*4882a593Smuzhiyun #define PCLK_CPUEMADET 286 349*4882a593Smuzhiyun #define PCLK_DDRPHY 287 350*4882a593Smuzhiyun #define PCLK_DSIPHY 289 351*4882a593Smuzhiyun #define PCLK_CSIPHY0 290 352*4882a593Smuzhiyun #define PCLK_CSIPHY1 291 353*4882a593Smuzhiyun #define PCLK_USBPHY_HOST 292 354*4882a593Smuzhiyun #define PCLK_USBPHY_OTG 293 355*4882a593Smuzhiyun #define PCLK_OTP 294 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun #define CLK_NR_CLKS (PCLK_OTP + 1) 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun /* pmu soft-reset indices */ 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun /* pmu_cru_softrst_con0 */ 362*4882a593Smuzhiyun #define SRST_PDPMU_NIU_P 0 363*4882a593Smuzhiyun #define SRST_PMU_SGRF_P 1 364*4882a593Smuzhiyun #define SRST_PMU_SGRF_REMAP_P 2 365*4882a593Smuzhiyun #define SRST_I2C0_P 3 366*4882a593Smuzhiyun #define SRST_I2C0 4 367*4882a593Smuzhiyun #define SRST_I2C2_P 7 368*4882a593Smuzhiyun #define SRST_I2C2 8 369*4882a593Smuzhiyun #define SRST_UART1_P 9 370*4882a593Smuzhiyun #define SRST_UART1 10 371*4882a593Smuzhiyun #define SRST_PWM0_P 11 372*4882a593Smuzhiyun #define SRST_PWM0 12 373*4882a593Smuzhiyun #define SRST_PWM1_P 13 374*4882a593Smuzhiyun #define SRST_PWM1 14 375*4882a593Smuzhiyun #define SRST_DDR_FAIL_SAFE 15 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun /* pmu_cru_softrst_con1 */ 378*4882a593Smuzhiyun #define SRST_GPIO0_P 17 379*4882a593Smuzhiyun #define SRST_GPIO0_DB 18 380*4882a593Smuzhiyun #define SRST_SPI0_P 19 381*4882a593Smuzhiyun #define SRST_SPI0 20 382*4882a593Smuzhiyun #define SRST_PMUGRF_P 21 383*4882a593Smuzhiyun #define SRST_CHIPVEROTP_P 22 384*4882a593Smuzhiyun #define SRST_PMUPVTM 24 385*4882a593Smuzhiyun #define SRST_PMUPVTM_P 25 386*4882a593Smuzhiyun #define SRST_PMUCRU_P 30 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun /* soft-reset indices */ 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun /* cru_softrst_con0 */ 391*4882a593Smuzhiyun #define SRST_CORE0_PO 0 392*4882a593Smuzhiyun #define SRST_CORE1_PO 1 393*4882a593Smuzhiyun #define SRST_CORE2_PO 2 394*4882a593Smuzhiyun #define SRST_CORE3_PO 3 395*4882a593Smuzhiyun #define SRST_CORE0 4 396*4882a593Smuzhiyun #define SRST_CORE1 5 397*4882a593Smuzhiyun #define SRST_CORE2 6 398*4882a593Smuzhiyun #define SRST_CORE3 7 399*4882a593Smuzhiyun #define SRST_CORE0_DBG 8 400*4882a593Smuzhiyun #define SRST_CORE1_DBG 9 401*4882a593Smuzhiyun #define SRST_CORE2_DBG 10 402*4882a593Smuzhiyun #define SRST_CORE3_DBG 11 403*4882a593Smuzhiyun #define SRST_NL2 12 404*4882a593Smuzhiyun #define SRST_CORE_NIU_A 13 405*4882a593Smuzhiyun #define SRST_DBG_DAPLITE_P 14 406*4882a593Smuzhiyun #define SRST_DAPLITE_P 15 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun /* cru_softrst_con1 */ 409*4882a593Smuzhiyun #define SRST_PDBUS_NIU1_A 16 410*4882a593Smuzhiyun #define SRST_PDBUS_NIU1_H 17 411*4882a593Smuzhiyun #define SRST_PDBUS_NIU1_P 18 412*4882a593Smuzhiyun #define SRST_PDBUS_NIU2_A 19 413*4882a593Smuzhiyun #define SRST_PDBUS_NIU2_H 20 414*4882a593Smuzhiyun #define SRST_PDBUS_NIU3_A 21 415*4882a593Smuzhiyun #define SRST_PDBUS_NIU3_H 22 416*4882a593Smuzhiyun #define SRST_PDBUS_HOLD_NIU1_A 23 417*4882a593Smuzhiyun #define SRST_DBG_NIU_P 24 418*4882a593Smuzhiyun #define SRST_PDCORE_NIIU_H 25 419*4882a593Smuzhiyun #define SRST_MUC_NIU 26 420*4882a593Smuzhiyun #define SRST_DCF_A 29 421*4882a593Smuzhiyun #define SRST_DCF_P 30 422*4882a593Smuzhiyun #define SRST_SYSTEM_SRAM_A 31 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun /* cru_softrst_con2 */ 425*4882a593Smuzhiyun #define SRST_I2C1_P 32 426*4882a593Smuzhiyun #define SRST_I2C1 33 427*4882a593Smuzhiyun #define SRST_I2C3_P 34 428*4882a593Smuzhiyun #define SRST_I2C3 35 429*4882a593Smuzhiyun #define SRST_I2C4_P 36 430*4882a593Smuzhiyun #define SRST_I2C4 37 431*4882a593Smuzhiyun #define SRST_I2C5_P 38 432*4882a593Smuzhiyun #define SRST_I2C5 39 433*4882a593Smuzhiyun #define SRST_SPI1_P 40 434*4882a593Smuzhiyun #define SRST_SPI1 41 435*4882a593Smuzhiyun #define SRST_MCU_CORE 42 436*4882a593Smuzhiyun #define SRST_PWM2_P 44 437*4882a593Smuzhiyun #define SRST_PWM2 45 438*4882a593Smuzhiyun #define SRST_SPINLOCK_A 46 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun /* cru_softrst_con3 */ 441*4882a593Smuzhiyun #define SRST_UART0_P 48 442*4882a593Smuzhiyun #define SRST_UART0 49 443*4882a593Smuzhiyun #define SRST_UART2_P 50 444*4882a593Smuzhiyun #define SRST_UART2 51 445*4882a593Smuzhiyun #define SRST_UART3_P 52 446*4882a593Smuzhiyun #define SRST_UART3 53 447*4882a593Smuzhiyun #define SRST_UART4_P 54 448*4882a593Smuzhiyun #define SRST_UART4 55 449*4882a593Smuzhiyun #define SRST_UART5_P 56 450*4882a593Smuzhiyun #define SRST_UART5 57 451*4882a593Smuzhiyun #define SRST_WDT_P 58 452*4882a593Smuzhiyun #define SRST_SARADC_P 59 453*4882a593Smuzhiyun #define SRST_GRF_P 61 454*4882a593Smuzhiyun #define SRST_TIMER_P 62 455*4882a593Smuzhiyun #define SRST_MAILBOX_P 63 456*4882a593Smuzhiyun 457*4882a593Smuzhiyun /* cru_softrst_con4 */ 458*4882a593Smuzhiyun #define SRST_TIMER0 64 459*4882a593Smuzhiyun #define SRST_TIMER1 65 460*4882a593Smuzhiyun #define SRST_TIMER2 66 461*4882a593Smuzhiyun #define SRST_TIMER3 67 462*4882a593Smuzhiyun #define SRST_TIMER4 68 463*4882a593Smuzhiyun #define SRST_TIMER5 69 464*4882a593Smuzhiyun #define SRST_INTMUX_P 70 465*4882a593Smuzhiyun #define SRST_GPIO1_P 72 466*4882a593Smuzhiyun #define SRST_GPIO1_DB 73 467*4882a593Smuzhiyun #define SRST_GPIO2_P 74 468*4882a593Smuzhiyun #define SRST_GPIO2_DB 75 469*4882a593Smuzhiyun #define SRST_GPIO3_P 76 470*4882a593Smuzhiyun #define SRST_GPIO3_DB 77 471*4882a593Smuzhiyun #define SRST_GPIO4_P 78 472*4882a593Smuzhiyun #define SRST_GPIO4_DB 79 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun /* cru_softrst_con5 */ 475*4882a593Smuzhiyun #define SRST_CAN_P 80 476*4882a593Smuzhiyun #define SRST_CAN 81 477*4882a593Smuzhiyun #define SRST_DECOM_A 85 478*4882a593Smuzhiyun #define SRST_DECOM_P 86 479*4882a593Smuzhiyun #define SRST_DECOM_D 87 480*4882a593Smuzhiyun #define SRST_PDCRYPTO_NIU_A 88 481*4882a593Smuzhiyun #define SRST_PDCRYPTO_NIU_H 89 482*4882a593Smuzhiyun #define SRST_CRYPTO_A 90 483*4882a593Smuzhiyun #define SRST_CRYPTO_H 91 484*4882a593Smuzhiyun #define SRST_CRYPTO_CORE 92 485*4882a593Smuzhiyun #define SRST_CRYPTO_PKA 93 486*4882a593Smuzhiyun #define SRST_SGRF_P 95 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun /* cru_softrst_con6 */ 489*4882a593Smuzhiyun #define SRST_PDAUDIO_NIU_H 96 490*4882a593Smuzhiyun #define SRST_PDAUDIO_NIU_P 97 491*4882a593Smuzhiyun #define SRST_I2S0_H 98 492*4882a593Smuzhiyun #define SRST_I2S0_TX_M 99 493*4882a593Smuzhiyun #define SRST_I2S0_RX_M 100 494*4882a593Smuzhiyun #define SRST_I2S1_H 101 495*4882a593Smuzhiyun #define SRST_I2S1_M 102 496*4882a593Smuzhiyun #define SRST_I2S2_H 103 497*4882a593Smuzhiyun #define SRST_I2S2_M 104 498*4882a593Smuzhiyun #define SRST_PDM_H 105 499*4882a593Smuzhiyun #define SRST_PDM_M 106 500*4882a593Smuzhiyun #define SRST_AUDPWM_H 107 501*4882a593Smuzhiyun #define SRST_AUDPWM 108 502*4882a593Smuzhiyun #define SRST_ACDCDIG_P 109 503*4882a593Smuzhiyun #define SRST_ACDCDIG 110 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun /* cru_softrst_con7 */ 506*4882a593Smuzhiyun #define SRST_PDVEPU_NIU_A 112 507*4882a593Smuzhiyun #define SRST_PDVEPU_NIU_H 113 508*4882a593Smuzhiyun #define SRST_VENC_A 114 509*4882a593Smuzhiyun #define SRST_VENC_H 115 510*4882a593Smuzhiyun #define SRST_VENC_CORE 116 511*4882a593Smuzhiyun #define SRST_PDVDEC_NIU_A 117 512*4882a593Smuzhiyun #define SRST_PDVDEC_NIU_H 118 513*4882a593Smuzhiyun #define SRST_VDEC_A 119 514*4882a593Smuzhiyun #define SRST_VDEC_H 120 515*4882a593Smuzhiyun #define SRST_VDEC_CORE 121 516*4882a593Smuzhiyun #define SRST_VDEC_CA 122 517*4882a593Smuzhiyun #define SRST_VDEC_HEVC_CA 123 518*4882a593Smuzhiyun #define SRST_PDJPEG_NIU_A 124 519*4882a593Smuzhiyun #define SRST_PDJPEG_NIU_H 125 520*4882a593Smuzhiyun #define SRST_JPEG_A 126 521*4882a593Smuzhiyun #define SRST_JPEG_H 127 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun /* cru_softrst_con8 */ 524*4882a593Smuzhiyun #define SRST_PDVO_NIU_A 128 525*4882a593Smuzhiyun #define SRST_PDVO_NIU_H 129 526*4882a593Smuzhiyun #define SRST_PDVO_NIU_P 130 527*4882a593Smuzhiyun #define SRST_RGA_A 131 528*4882a593Smuzhiyun #define SRST_RGA_H 132 529*4882a593Smuzhiyun #define SRST_RGA_CORE 133 530*4882a593Smuzhiyun #define SRST_VOP_A 134 531*4882a593Smuzhiyun #define SRST_VOP_H 135 532*4882a593Smuzhiyun #define SRST_VOP_D 136 533*4882a593Smuzhiyun #define SRST_TXBYTEHS_DSIHOST 137 534*4882a593Smuzhiyun #define SRST_DSIHOST_P 138 535*4882a593Smuzhiyun #define SRST_IEP_A 139 536*4882a593Smuzhiyun #define SRST_IEP_H 140 537*4882a593Smuzhiyun #define SRST_IEP_CORE 141 538*4882a593Smuzhiyun #define SRST_ISP_RX_P 142 539*4882a593Smuzhiyun 540*4882a593Smuzhiyun /* cru_softrst_con9 */ 541*4882a593Smuzhiyun #define SRST_PDVI_NIU_A 144 542*4882a593Smuzhiyun #define SRST_PDVI_NIU_H 145 543*4882a593Smuzhiyun #define SRST_PDVI_NIU_P 146 544*4882a593Smuzhiyun #define SRST_ISP 147 545*4882a593Smuzhiyun #define SRST_CIF_A 148 546*4882a593Smuzhiyun #define SRST_CIF_H 149 547*4882a593Smuzhiyun #define SRST_CIF_D 150 548*4882a593Smuzhiyun #define SRST_CIF_P 151 549*4882a593Smuzhiyun #define SRST_CIF_I 152 550*4882a593Smuzhiyun #define SRST_CIF_RX_P 153 551*4882a593Smuzhiyun #define SRST_PDISPP_NIU_A 154 552*4882a593Smuzhiyun #define SRST_PDISPP_NIU_H 155 553*4882a593Smuzhiyun #define SRST_ISPP_A 156 554*4882a593Smuzhiyun #define SRST_ISPP_H 157 555*4882a593Smuzhiyun #define SRST_ISPP 158 556*4882a593Smuzhiyun #define SRST_CSIHOST_P 159 557*4882a593Smuzhiyun 558*4882a593Smuzhiyun /* cru_softrst_con10 */ 559*4882a593Smuzhiyun #define SRST_PDPHPMID_NIU_A 160 560*4882a593Smuzhiyun #define SRST_PDPHPMID_NIU_H 161 561*4882a593Smuzhiyun #define SRST_PDNVM_NIU_H 163 562*4882a593Smuzhiyun #define SRST_SDMMC_H 164 563*4882a593Smuzhiyun #define SRST_SDIO_H 165 564*4882a593Smuzhiyun #define SRST_EMMC_H 166 565*4882a593Smuzhiyun #define SRST_SFC_H 167 566*4882a593Smuzhiyun #define SRST_SFCXIP_H 168 567*4882a593Smuzhiyun #define SRST_SFC 169 568*4882a593Smuzhiyun #define SRST_NANDC_H 170 569*4882a593Smuzhiyun #define SRST_NANDC 171 570*4882a593Smuzhiyun #define SRST_PDSDMMC_H 173 571*4882a593Smuzhiyun #define SRST_PDSDIO_H 174 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun /* cru_softrst_con11 */ 574*4882a593Smuzhiyun #define SRST_PDUSB_NIU_A 176 575*4882a593Smuzhiyun #define SRST_PDUSB_NIU_H 177 576*4882a593Smuzhiyun #define SRST_USBHOST_H 178 577*4882a593Smuzhiyun #define SRST_USBHOST_ARB_H 179 578*4882a593Smuzhiyun #define SRST_USBHOST_UTMI 180 579*4882a593Smuzhiyun #define SRST_USBOTG_A 181 580*4882a593Smuzhiyun #define SRST_USBPHY_OTG_P 182 581*4882a593Smuzhiyun #define SRST_USBPHY_HOST_P 183 582*4882a593Smuzhiyun #define SRST_USBPHYPOR_OTG 184 583*4882a593Smuzhiyun #define SRST_USBPHYPOR_HOST 185 584*4882a593Smuzhiyun #define SRST_PDGMAC_NIU_A 188 585*4882a593Smuzhiyun #define SRST_PDGMAC_NIU_P 189 586*4882a593Smuzhiyun #define SRST_GMAC_A 190 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun /* cru_softrst_con12 */ 589*4882a593Smuzhiyun #define SRST_DDR_DFICTL_P 193 590*4882a593Smuzhiyun #define SRST_DDR_MON_P 194 591*4882a593Smuzhiyun #define SRST_DDR_STANDBY_P 195 592*4882a593Smuzhiyun #define SRST_DDR_GRF_P 196 593*4882a593Smuzhiyun #define SRST_DDR_MSCH_P 197 594*4882a593Smuzhiyun #define SRST_DDR_SPLIT_A 198 595*4882a593Smuzhiyun #define SRST_DDR_MSCH 199 596*4882a593Smuzhiyun #define SRST_DDR_DFICTL 202 597*4882a593Smuzhiyun #define SRST_DDR_STANDBY 203 598*4882a593Smuzhiyun #define SRST_NPUMCU_NIU 205 599*4882a593Smuzhiyun #define SRST_DDRPHY_P 206 600*4882a593Smuzhiyun #define SRST_DDRPHY 207 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun /* cru_softrst_con13 */ 603*4882a593Smuzhiyun #define SRST_PDNPU_NIU_A 208 604*4882a593Smuzhiyun #define SRST_PDNPU_NIU_H 209 605*4882a593Smuzhiyun #define SRST_PDNPU_NIU_P 210 606*4882a593Smuzhiyun #define SRST_NPU_A 211 607*4882a593Smuzhiyun #define SRST_NPU_H 212 608*4882a593Smuzhiyun #define SRST_NPU 213 609*4882a593Smuzhiyun #define SRST_NPUPVTM_P 214 610*4882a593Smuzhiyun #define SRST_NPUPVTM 215 611*4882a593Smuzhiyun #define SRST_NPU_TSADC_P 216 612*4882a593Smuzhiyun #define SRST_NPU_TSADC 217 613*4882a593Smuzhiyun #define SRST_NPU_TSADCPHY 218 614*4882a593Smuzhiyun #define SRST_CIFLITE_A 220 615*4882a593Smuzhiyun #define SRST_CIFLITE_H 221 616*4882a593Smuzhiyun #define SRST_CIFLITE_D 222 617*4882a593Smuzhiyun #define SRST_CIFLITE_RX_P 223 618*4882a593Smuzhiyun 619*4882a593Smuzhiyun /* cru_softrst_con14 */ 620*4882a593Smuzhiyun #define SRST_TOPNIU_P 224 621*4882a593Smuzhiyun #define SRST_TOPCRU_P 225 622*4882a593Smuzhiyun #define SRST_TOPGRF_P 226 623*4882a593Smuzhiyun #define SRST_CPUEMADET_P 227 624*4882a593Smuzhiyun #define SRST_CSIPHY0_P 228 625*4882a593Smuzhiyun #define SRST_CSIPHY1_P 229 626*4882a593Smuzhiyun #define SRST_DSIPHY_P 230 627*4882a593Smuzhiyun #define SRST_CPU_TSADC_P 232 628*4882a593Smuzhiyun #define SRST_CPU_TSADC 233 629*4882a593Smuzhiyun #define SRST_CPU_TSADCPHY 234 630*4882a593Smuzhiyun #define SRST_CPUPVTM_P 235 631*4882a593Smuzhiyun #define SRST_CPUPVTM 236 632*4882a593Smuzhiyun 633*4882a593Smuzhiyun #endif 634