1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2017 ROCKCHIP, Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This software is licensed under the terms of the GNU General Public 6*4882a593Smuzhiyun * License version 2, as published by the Free Software Foundation, and 7*4882a593Smuzhiyun * may be copied, distributed, and modified under those terms. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 10*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*4882a593Smuzhiyun * GNU General Public License for more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H 17*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define DDR2_DEFAULT (0) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define DDR3_800D (0) /* 5-5-5 */ 22*4882a593Smuzhiyun #define DDR3_800E (1) /* 6-6-6 */ 23*4882a593Smuzhiyun #define DDR3_1066E (2) /* 6-6-6 */ 24*4882a593Smuzhiyun #define DDR3_1066F (3) /* 7-7-7 */ 25*4882a593Smuzhiyun #define DDR3_1066G (4) /* 8-8-8 */ 26*4882a593Smuzhiyun #define DDR3_1333F (5) /* 7-7-7 */ 27*4882a593Smuzhiyun #define DDR3_1333G (6) /* 8-8-8 */ 28*4882a593Smuzhiyun #define DDR3_1333H (7) /* 9-9-9 */ 29*4882a593Smuzhiyun #define DDR3_1333J (8) /* 10-10-10 */ 30*4882a593Smuzhiyun #define DDR3_1600G (9) /* 8-8-8 */ 31*4882a593Smuzhiyun #define DDR3_1600H (10) /* 9-9-9 */ 32*4882a593Smuzhiyun #define DDR3_1600J (11) /* 10-10-10 */ 33*4882a593Smuzhiyun #define DDR3_1600K (12) /* 11-11-11 */ 34*4882a593Smuzhiyun #define DDR3_1866J (13) /* 10-10-10 */ 35*4882a593Smuzhiyun #define DDR3_1866K (14) /* 11-11-11 */ 36*4882a593Smuzhiyun #define DDR3_1866L (15) /* 12-12-12 */ 37*4882a593Smuzhiyun #define DDR3_1866M (16) /* 13-13-13 */ 38*4882a593Smuzhiyun #define DDR3_2133K (17) /* 11-11-11 */ 39*4882a593Smuzhiyun #define DDR3_2133L (18) /* 12-12-12 */ 40*4882a593Smuzhiyun #define DDR3_2133M (19) /* 13-13-13 */ 41*4882a593Smuzhiyun #define DDR3_2133N (20) /* 14-14-14 */ 42*4882a593Smuzhiyun #define DDR3_DEFAULT (21) 43*4882a593Smuzhiyun #define DDR_DDR2 (22) 44*4882a593Smuzhiyun #define DDR_LPDDR (23) 45*4882a593Smuzhiyun #define DDR_LPDDR2 (24) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define DDR4_1600J (0) /* 10-10-10 */ 48*4882a593Smuzhiyun #define DDR4_1600K (1) /* 11-11-11 */ 49*4882a593Smuzhiyun #define DDR4_1600L (2) /* 12-12-12 */ 50*4882a593Smuzhiyun #define DDR4_1866L (3) /* 12-12-12 */ 51*4882a593Smuzhiyun #define DDR4_1866M (4) /* 13-13-13 */ 52*4882a593Smuzhiyun #define DDR4_1866N (5) /* 14-14-14 */ 53*4882a593Smuzhiyun #define DDR4_2133N (6) /* 14-14-14 */ 54*4882a593Smuzhiyun #define DDR4_2133P (7) /* 15-15-15 */ 55*4882a593Smuzhiyun #define DDR4_2133R (8) /* 16-16-16 */ 56*4882a593Smuzhiyun #define DDR4_2400P (9) /* 15-15-15 */ 57*4882a593Smuzhiyun #define DDR4_2400R (10) /* 16-16-16 */ 58*4882a593Smuzhiyun #define DDR4_2400U (11) /* 18-18-18 */ 59*4882a593Smuzhiyun #define DDR4_DEFAULT (12) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define PAUSE_CPU_STACK_SIZE 16 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #endif 64