1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Wyon Bi <bivvy.bi@rock-chips.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _RK628_CGU_H 9*4882a593Smuzhiyun #define _RK628_CGU_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CGU_CLK_CPLL 1 12*4882a593Smuzhiyun #define CGU_CLK_GPLL 2 13*4882a593Smuzhiyun #define CGU_CLK_CPLL_MUX 3 14*4882a593Smuzhiyun #define CGU_CLK_GPLL_MUX 4 15*4882a593Smuzhiyun #define CGU_PCLK_GPIO0 5 16*4882a593Smuzhiyun #define CGU_PCLK_GPIO1 6 17*4882a593Smuzhiyun #define CGU_PCLK_GPIO2 7 18*4882a593Smuzhiyun #define CGU_PCLK_GPIO3 8 19*4882a593Smuzhiyun #define CGU_PCLK_TXPHY_CON 9 20*4882a593Smuzhiyun #define CGU_PCLK_EFUSE 10 21*4882a593Smuzhiyun #define CGU_PCLK_DSI0 11 22*4882a593Smuzhiyun #define CGU_PCLK_DSI1 12 23*4882a593Smuzhiyun #define CGU_PCLK_CSI 13 24*4882a593Smuzhiyun #define CGU_PCLK_HDMITX 14 25*4882a593Smuzhiyun #define CGU_PCLK_RXPHY 15 26*4882a593Smuzhiyun #define CGU_PCLK_HDMIRX 16 27*4882a593Smuzhiyun #define CGU_PCLK_DPRX 17 28*4882a593Smuzhiyun #define CGU_PCLK_GVIHOST 18 29*4882a593Smuzhiyun #define CGU_CLK_CFG_DPHY0 19 30*4882a593Smuzhiyun #define CGU_CLK_CFG_DPHY1 20 31*4882a593Smuzhiyun #define CGU_CLK_TXESC 21 32*4882a593Smuzhiyun #define CGU_CLK_DPRX_VID 22 33*4882a593Smuzhiyun #define CGU_CLK_IMODET 23 34*4882a593Smuzhiyun #define CGU_CLK_HDMIRX_AUD 24 35*4882a593Smuzhiyun #define CGU_CLK_HDMIRX_CEC 25 36*4882a593Smuzhiyun #define CGU_CLK_RX_READ 26 37*4882a593Smuzhiyun #define CGU_SCLK_VOP 27 38*4882a593Smuzhiyun #define CGU_PCLK_LOGIC 28 39*4882a593Smuzhiyun #define CGU_CLK_GPIO_DB0 29 40*4882a593Smuzhiyun #define CGU_CLK_GPIO_DB1 30 41*4882a593Smuzhiyun #define CGU_CLK_GPIO_DB2 31 42*4882a593Smuzhiyun #define CGU_CLK_GPIO_DB3 32 43*4882a593Smuzhiyun #define CGU_CLK_I2S_8CH_SRC 33 44*4882a593Smuzhiyun #define CGU_CLK_I2S_8CH_FRAC 34 45*4882a593Smuzhiyun #define CGU_MCLK_I2S_8CH 35 46*4882a593Smuzhiyun #define CGU_I2S_MCLKOUT 36 47*4882a593Smuzhiyun #define CGU_BT1120DEC 37 48*4882a593Smuzhiyun #define CGU_CLK_TESTOUT 38 49*4882a593Smuzhiyun #define CGU_NR_CLKS 39 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #endif 52