1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * R9A06G032 sysctrl IDs 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2018 Renesas Electronics Europe Limited 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__ 11*4882a593Smuzhiyun #define __DT_BINDINGS_R9A06G032_SYSCTRL_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define R9A06G032_CLK_PLL_USB 1 14*4882a593Smuzhiyun #define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */ 15*4882a593Smuzhiyun #define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */ 16*4882a593Smuzhiyun #define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */ 17*4882a593Smuzhiyun #define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */ 18*4882a593Smuzhiyun #define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */ 19*4882a593Smuzhiyun #define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */ 20*4882a593Smuzhiyun #define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */ 21*4882a593Smuzhiyun #define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */ 22*4882a593Smuzhiyun #define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */ 23*4882a593Smuzhiyun #define R9A06G032_CLK_25_PG4 26 24*4882a593Smuzhiyun #define R9A06G032_CLK_25_PG5 27 25*4882a593Smuzhiyun #define R9A06G032_CLK_25_PG6 28 26*4882a593Smuzhiyun #define R9A06G032_CLK_25_PG7 29 27*4882a593Smuzhiyun #define R9A06G032_CLK_25_PG8 30 28*4882a593Smuzhiyun #define R9A06G032_CLK_ADC 31 29*4882a593Smuzhiyun #define R9A06G032_CLK_ECAT100 32 30*4882a593Smuzhiyun #define R9A06G032_CLK_HSR100 33 31*4882a593Smuzhiyun #define R9A06G032_CLK_I2C0 34 32*4882a593Smuzhiyun #define R9A06G032_CLK_I2C1 35 33*4882a593Smuzhiyun #define R9A06G032_CLK_MII_REF 36 34*4882a593Smuzhiyun #define R9A06G032_CLK_NAND 37 35*4882a593Smuzhiyun #define R9A06G032_CLK_NOUSBP2_PG6 38 36*4882a593Smuzhiyun #define R9A06G032_CLK_P1_PG2 39 37*4882a593Smuzhiyun #define R9A06G032_CLK_P1_PG3 40 38*4882a593Smuzhiyun #define R9A06G032_CLK_P1_PG4 41 39*4882a593Smuzhiyun #define R9A06G032_CLK_P4_PG3 42 40*4882a593Smuzhiyun #define R9A06G032_CLK_P4_PG4 43 41*4882a593Smuzhiyun #define R9A06G032_CLK_P6_PG1 44 42*4882a593Smuzhiyun #define R9A06G032_CLK_P6_PG2 45 43*4882a593Smuzhiyun #define R9A06G032_CLK_P6_PG3 46 44*4882a593Smuzhiyun #define R9A06G032_CLK_P6_PG4 47 45*4882a593Smuzhiyun #define R9A06G032_CLK_PCI_USB 48 46*4882a593Smuzhiyun #define R9A06G032_CLK_QSPI0 49 47*4882a593Smuzhiyun #define R9A06G032_CLK_QSPI1 50 48*4882a593Smuzhiyun #define R9A06G032_CLK_RGMII_REF 51 49*4882a593Smuzhiyun #define R9A06G032_CLK_RMII_REF 52 50*4882a593Smuzhiyun #define R9A06G032_CLK_SDIO0 53 51*4882a593Smuzhiyun #define R9A06G032_CLK_SDIO1 54 52*4882a593Smuzhiyun #define R9A06G032_CLK_SERCOS100 55 53*4882a593Smuzhiyun #define R9A06G032_CLK_SLCD 56 54*4882a593Smuzhiyun #define R9A06G032_CLK_SPI0 57 55*4882a593Smuzhiyun #define R9A06G032_CLK_SPI1 58 56*4882a593Smuzhiyun #define R9A06G032_CLK_SPI2 59 57*4882a593Smuzhiyun #define R9A06G032_CLK_SPI3 60 58*4882a593Smuzhiyun #define R9A06G032_CLK_SPI4 61 59*4882a593Smuzhiyun #define R9A06G032_CLK_SPI5 62 60*4882a593Smuzhiyun #define R9A06G032_CLK_SWITCH 63 61*4882a593Smuzhiyun #define R9A06G032_HCLK_ECAT125 65 62*4882a593Smuzhiyun #define R9A06G032_HCLK_PINCONFIG 66 63*4882a593Smuzhiyun #define R9A06G032_HCLK_SERCOS 67 64*4882a593Smuzhiyun #define R9A06G032_HCLK_SGPIO2 68 65*4882a593Smuzhiyun #define R9A06G032_HCLK_SGPIO3 69 66*4882a593Smuzhiyun #define R9A06G032_HCLK_SGPIO4 70 67*4882a593Smuzhiyun #define R9A06G032_HCLK_TIMER0 71 68*4882a593Smuzhiyun #define R9A06G032_HCLK_TIMER1 72 69*4882a593Smuzhiyun #define R9A06G032_HCLK_USBF 73 70*4882a593Smuzhiyun #define R9A06G032_HCLK_USBH 74 71*4882a593Smuzhiyun #define R9A06G032_HCLK_USBPM 75 72*4882a593Smuzhiyun #define R9A06G032_CLK_48_PG_F 76 73*4882a593Smuzhiyun #define R9A06G032_CLK_48_PG4 77 74*4882a593Smuzhiyun #define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */ 75*4882a593Smuzhiyun #define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */ 76*4882a593Smuzhiyun #define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */ 77*4882a593Smuzhiyun #define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */ 78*4882a593Smuzhiyun #define R9A06G032_HCLK_CAN0 85 79*4882a593Smuzhiyun #define R9A06G032_HCLK_CAN1 86 80*4882a593Smuzhiyun #define R9A06G032_HCLK_DELTASIGMA 87 81*4882a593Smuzhiyun #define R9A06G032_HCLK_PWMPTO 88 82*4882a593Smuzhiyun #define R9A06G032_HCLK_RSV 89 83*4882a593Smuzhiyun #define R9A06G032_HCLK_SGPIO0 90 84*4882a593Smuzhiyun #define R9A06G032_HCLK_SGPIO1 91 85*4882a593Smuzhiyun #define R9A06G032_RTOS_MDC 92 86*4882a593Smuzhiyun #define R9A06G032_CLK_CM3 93 87*4882a593Smuzhiyun #define R9A06G032_CLK_DDRC 94 88*4882a593Smuzhiyun #define R9A06G032_CLK_ECAT25 95 89*4882a593Smuzhiyun #define R9A06G032_CLK_HSR50 96 90*4882a593Smuzhiyun #define R9A06G032_CLK_HW_RTOS 97 91*4882a593Smuzhiyun #define R9A06G032_CLK_SERCOS50 98 92*4882a593Smuzhiyun #define R9A06G032_HCLK_ADC 99 93*4882a593Smuzhiyun #define R9A06G032_HCLK_CM3 100 94*4882a593Smuzhiyun #define R9A06G032_HCLK_CRYPTO_EIP150 101 95*4882a593Smuzhiyun #define R9A06G032_HCLK_CRYPTO_EIP93 102 96*4882a593Smuzhiyun #define R9A06G032_HCLK_DDRC 103 97*4882a593Smuzhiyun #define R9A06G032_HCLK_DMA0 104 98*4882a593Smuzhiyun #define R9A06G032_HCLK_DMA1 105 99*4882a593Smuzhiyun #define R9A06G032_HCLK_GMAC0 106 100*4882a593Smuzhiyun #define R9A06G032_HCLK_GMAC1 107 101*4882a593Smuzhiyun #define R9A06G032_HCLK_GPIO0 108 102*4882a593Smuzhiyun #define R9A06G032_HCLK_GPIO1 109 103*4882a593Smuzhiyun #define R9A06G032_HCLK_GPIO2 110 104*4882a593Smuzhiyun #define R9A06G032_HCLK_HSR 111 105*4882a593Smuzhiyun #define R9A06G032_HCLK_I2C0 112 106*4882a593Smuzhiyun #define R9A06G032_HCLK_I2C1 113 107*4882a593Smuzhiyun #define R9A06G032_HCLK_LCD 114 108*4882a593Smuzhiyun #define R9A06G032_HCLK_MSEBI_M 115 109*4882a593Smuzhiyun #define R9A06G032_HCLK_MSEBI_S 116 110*4882a593Smuzhiyun #define R9A06G032_HCLK_NAND 117 111*4882a593Smuzhiyun #define R9A06G032_HCLK_PG_I 118 112*4882a593Smuzhiyun #define R9A06G032_HCLK_PG19 119 113*4882a593Smuzhiyun #define R9A06G032_HCLK_PG20 120 114*4882a593Smuzhiyun #define R9A06G032_HCLK_PG3 121 115*4882a593Smuzhiyun #define R9A06G032_HCLK_PG4 122 116*4882a593Smuzhiyun #define R9A06G032_HCLK_QSPI0 123 117*4882a593Smuzhiyun #define R9A06G032_HCLK_QSPI1 124 118*4882a593Smuzhiyun #define R9A06G032_HCLK_ROM 125 119*4882a593Smuzhiyun #define R9A06G032_HCLK_RTC 126 120*4882a593Smuzhiyun #define R9A06G032_HCLK_SDIO0 127 121*4882a593Smuzhiyun #define R9A06G032_HCLK_SDIO1 128 122*4882a593Smuzhiyun #define R9A06G032_HCLK_SEMAP 129 123*4882a593Smuzhiyun #define R9A06G032_HCLK_SPI0 130 124*4882a593Smuzhiyun #define R9A06G032_HCLK_SPI1 131 125*4882a593Smuzhiyun #define R9A06G032_HCLK_SPI2 132 126*4882a593Smuzhiyun #define R9A06G032_HCLK_SPI3 133 127*4882a593Smuzhiyun #define R9A06G032_HCLK_SPI4 134 128*4882a593Smuzhiyun #define R9A06G032_HCLK_SPI5 135 129*4882a593Smuzhiyun #define R9A06G032_HCLK_SWITCH 136 130*4882a593Smuzhiyun #define R9A06G032_HCLK_SWITCH_RG 137 131*4882a593Smuzhiyun #define R9A06G032_HCLK_UART0 138 132*4882a593Smuzhiyun #define R9A06G032_HCLK_UART1 139 133*4882a593Smuzhiyun #define R9A06G032_HCLK_UART2 140 134*4882a593Smuzhiyun #define R9A06G032_HCLK_UART3 141 135*4882a593Smuzhiyun #define R9A06G032_HCLK_UART4 142 136*4882a593Smuzhiyun #define R9A06G032_HCLK_UART5 143 137*4882a593Smuzhiyun #define R9A06G032_HCLK_UART6 144 138*4882a593Smuzhiyun #define R9A06G032_HCLK_UART7 145 139*4882a593Smuzhiyun #define R9A06G032_CLK_UART0 146 140*4882a593Smuzhiyun #define R9A06G032_CLK_UART1 147 141*4882a593Smuzhiyun #define R9A06G032_CLK_UART2 148 142*4882a593Smuzhiyun #define R9A06G032_CLK_UART3 149 143*4882a593Smuzhiyun #define R9A06G032_CLK_UART4 150 144*4882a593Smuzhiyun #define R9A06G032_CLK_UART5 151 145*4882a593Smuzhiyun #define R9A06G032_CLK_UART6 152 146*4882a593Smuzhiyun #define R9A06G032_CLK_UART7 153 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */ 149