1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2020 Renesas Electronics Corp. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ 6*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* r8a779A0 CPG Core Clocks */ 11*4882a593Smuzhiyun #define R8A779A0_CLK_Z0 0 12*4882a593Smuzhiyun #define R8A779A0_CLK_ZX 1 13*4882a593Smuzhiyun #define R8A779A0_CLK_Z1 2 14*4882a593Smuzhiyun #define R8A779A0_CLK_ZR 3 15*4882a593Smuzhiyun #define R8A779A0_CLK_ZS 4 16*4882a593Smuzhiyun #define R8A779A0_CLK_ZT 5 17*4882a593Smuzhiyun #define R8A779A0_CLK_ZTR 6 18*4882a593Smuzhiyun #define R8A779A0_CLK_S1D1 7 19*4882a593Smuzhiyun #define R8A779A0_CLK_S1D2 8 20*4882a593Smuzhiyun #define R8A779A0_CLK_S1D4 9 21*4882a593Smuzhiyun #define R8A779A0_CLK_S1D8 10 22*4882a593Smuzhiyun #define R8A779A0_CLK_S1D12 11 23*4882a593Smuzhiyun #define R8A779A0_CLK_S3D1 12 24*4882a593Smuzhiyun #define R8A779A0_CLK_S3D2 13 25*4882a593Smuzhiyun #define R8A779A0_CLK_S3D4 14 26*4882a593Smuzhiyun #define R8A779A0_CLK_LB 15 27*4882a593Smuzhiyun #define R8A779A0_CLK_CP 16 28*4882a593Smuzhiyun #define R8A779A0_CLK_CL 17 29*4882a593Smuzhiyun #define R8A779A0_CLK_CL16MCK 18 30*4882a593Smuzhiyun #define R8A779A0_CLK_ZB30 19 31*4882a593Smuzhiyun #define R8A779A0_CLK_ZB30D2 20 32*4882a593Smuzhiyun #define R8A779A0_CLK_ZB30D4 21 33*4882a593Smuzhiyun #define R8A779A0_CLK_ZB31 22 34*4882a593Smuzhiyun #define R8A779A0_CLK_ZB31D2 23 35*4882a593Smuzhiyun #define R8A779A0_CLK_ZB31D4 24 36*4882a593Smuzhiyun #define R8A779A0_CLK_SD0H 25 37*4882a593Smuzhiyun #define R8A779A0_CLK_SD0 26 38*4882a593Smuzhiyun #define R8A779A0_CLK_RPC 27 39*4882a593Smuzhiyun #define R8A779A0_CLK_RPCD2 28 40*4882a593Smuzhiyun #define R8A779A0_CLK_MSO 29 41*4882a593Smuzhiyun #define R8A779A0_CLK_CANFD 30 42*4882a593Smuzhiyun #define R8A779A0_CLK_CSI0 31 43*4882a593Smuzhiyun #define R8A779A0_CLK_FRAY 32 44*4882a593Smuzhiyun #define R8A779A0_CLK_DSI 33 45*4882a593Smuzhiyun #define R8A779A0_CLK_VIP 34 46*4882a593Smuzhiyun #define R8A779A0_CLK_ADGH 35 47*4882a593Smuzhiyun #define R8A779A0_CLK_CNNDSP 36 48*4882a593Smuzhiyun #define R8A779A0_CLK_ICU 37 49*4882a593Smuzhiyun #define R8A779A0_CLK_ICUD2 38 50*4882a593Smuzhiyun #define R8A779A0_CLK_VCBUS 39 51*4882a593Smuzhiyun #define R8A779A0_CLK_CBFUSA 40 52*4882a593Smuzhiyun #define R8A779A0_CLK_R 41 53*4882a593Smuzhiyun #define R8A779A0_CLK_OSC 42 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */ 56