1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2017 Glider bvba 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ 6*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* r8a77995 CPG Core Clocks */ 11*4882a593Smuzhiyun #define R8A77995_CLK_Z2 0 12*4882a593Smuzhiyun #define R8A77995_CLK_ZG 1 13*4882a593Smuzhiyun #define R8A77995_CLK_ZTR 2 14*4882a593Smuzhiyun #define R8A77995_CLK_ZT 3 15*4882a593Smuzhiyun #define R8A77995_CLK_ZX 4 16*4882a593Smuzhiyun #define R8A77995_CLK_S0D1 5 17*4882a593Smuzhiyun #define R8A77995_CLK_S1D1 6 18*4882a593Smuzhiyun #define R8A77995_CLK_S1D2 7 19*4882a593Smuzhiyun #define R8A77995_CLK_S1D4 8 20*4882a593Smuzhiyun #define R8A77995_CLK_S2D1 9 21*4882a593Smuzhiyun #define R8A77995_CLK_S2D2 10 22*4882a593Smuzhiyun #define R8A77995_CLK_S2D4 11 23*4882a593Smuzhiyun #define R8A77995_CLK_S3D1 12 24*4882a593Smuzhiyun #define R8A77995_CLK_S3D2 13 25*4882a593Smuzhiyun #define R8A77995_CLK_S3D4 14 26*4882a593Smuzhiyun #define R8A77995_CLK_S1D4C 15 27*4882a593Smuzhiyun #define R8A77995_CLK_S3D1C 16 28*4882a593Smuzhiyun #define R8A77995_CLK_S3D2C 17 29*4882a593Smuzhiyun #define R8A77995_CLK_S3D4C 18 30*4882a593Smuzhiyun #define R8A77995_CLK_LB 19 31*4882a593Smuzhiyun #define R8A77995_CLK_CL 20 32*4882a593Smuzhiyun #define R8A77995_CLK_ZB3 21 33*4882a593Smuzhiyun #define R8A77995_CLK_ZB3D2 22 34*4882a593Smuzhiyun #define R8A77995_CLK_CR 23 35*4882a593Smuzhiyun #define R8A77995_CLK_CRD2 24 36*4882a593Smuzhiyun #define R8A77995_CLK_SD0H 25 37*4882a593Smuzhiyun #define R8A77995_CLK_SD0 26 38*4882a593Smuzhiyun /* CLK_SSP2 was removed */ 39*4882a593Smuzhiyun /* CLK_SSP1 was removed */ 40*4882a593Smuzhiyun #define R8A77995_CLK_RPC 29 41*4882a593Smuzhiyun #define R8A77995_CLK_RPCD2 30 42*4882a593Smuzhiyun #define R8A77995_CLK_ZA2 31 43*4882a593Smuzhiyun #define R8A77995_CLK_ZA8 32 44*4882a593Smuzhiyun #define R8A77995_CLK_Z2D 33 45*4882a593Smuzhiyun #define R8A77995_CLK_CANFD 34 46*4882a593Smuzhiyun #define R8A77995_CLK_MSO 35 47*4882a593Smuzhiyun #define R8A77995_CLK_R 36 48*4882a593Smuzhiyun #define R8A77995_CLK_OSC 37 49*4882a593Smuzhiyun #define R8A77995_CLK_LV0 38 50*4882a593Smuzhiyun #define R8A77995_CLK_LV1 39 51*4882a593Smuzhiyun #define R8A77995_CLK_CP 40 52*4882a593Smuzhiyun #define R8A77995_CLK_CPEX 41 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */ 55