1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2018 Renesas Electronics Corp. 4*4882a593Smuzhiyun * Copyright (C) 2018 Cogent Embedded, Inc. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* r8a77980 CPG Core Clocks */ 12*4882a593Smuzhiyun #define R8A77980_CLK_Z2 0 13*4882a593Smuzhiyun #define R8A77980_CLK_ZR 1 14*4882a593Smuzhiyun #define R8A77980_CLK_ZTR 2 15*4882a593Smuzhiyun #define R8A77980_CLK_ZTRD2 3 16*4882a593Smuzhiyun #define R8A77980_CLK_ZT 4 17*4882a593Smuzhiyun #define R8A77980_CLK_ZX 5 18*4882a593Smuzhiyun #define R8A77980_CLK_S0D1 6 19*4882a593Smuzhiyun #define R8A77980_CLK_S0D2 7 20*4882a593Smuzhiyun #define R8A77980_CLK_S0D3 8 21*4882a593Smuzhiyun #define R8A77980_CLK_S0D4 9 22*4882a593Smuzhiyun #define R8A77980_CLK_S0D6 10 23*4882a593Smuzhiyun #define R8A77980_CLK_S0D12 11 24*4882a593Smuzhiyun #define R8A77980_CLK_S0D24 12 25*4882a593Smuzhiyun #define R8A77980_CLK_S1D1 13 26*4882a593Smuzhiyun #define R8A77980_CLK_S1D2 14 27*4882a593Smuzhiyun #define R8A77980_CLK_S1D4 15 28*4882a593Smuzhiyun #define R8A77980_CLK_S2D1 16 29*4882a593Smuzhiyun #define R8A77980_CLK_S2D2 17 30*4882a593Smuzhiyun #define R8A77980_CLK_S2D4 18 31*4882a593Smuzhiyun #define R8A77980_CLK_S3D1 19 32*4882a593Smuzhiyun #define R8A77980_CLK_S3D2 20 33*4882a593Smuzhiyun #define R8A77980_CLK_S3D4 21 34*4882a593Smuzhiyun #define R8A77980_CLK_LB 22 35*4882a593Smuzhiyun #define R8A77980_CLK_CL 23 36*4882a593Smuzhiyun #define R8A77980_CLK_ZB3 24 37*4882a593Smuzhiyun #define R8A77980_CLK_ZB3D2 25 38*4882a593Smuzhiyun #define R8A77980_CLK_ZB3D4 26 39*4882a593Smuzhiyun #define R8A77980_CLK_SD0H 27 40*4882a593Smuzhiyun #define R8A77980_CLK_SD0 28 41*4882a593Smuzhiyun #define R8A77980_CLK_RPC 29 42*4882a593Smuzhiyun #define R8A77980_CLK_RPCD2 30 43*4882a593Smuzhiyun #define R8A77980_CLK_MSO 31 44*4882a593Smuzhiyun #define R8A77980_CLK_CANFD 32 45*4882a593Smuzhiyun #define R8A77980_CLK_CSI0 33 46*4882a593Smuzhiyun #define R8A77980_CLK_CP 34 47*4882a593Smuzhiyun #define R8A77980_CLK_CPEX 35 48*4882a593Smuzhiyun #define R8A77980_CLK_R 36 49*4882a593Smuzhiyun #define R8A77980_CLK_OSC 37 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */ 52