1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2016 Renesas Electronics Corp. 4*4882a593Smuzhiyun * Copyright (C) 2017 Cogent Embedded, Inc. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* r8a77970 CPG Core Clocks */ 12*4882a593Smuzhiyun #define R8A77970_CLK_Z2 0 13*4882a593Smuzhiyun #define R8A77970_CLK_ZR 1 14*4882a593Smuzhiyun #define R8A77970_CLK_ZTR 2 15*4882a593Smuzhiyun #define R8A77970_CLK_ZTRD2 3 16*4882a593Smuzhiyun #define R8A77970_CLK_ZT 4 17*4882a593Smuzhiyun #define R8A77970_CLK_ZX 5 18*4882a593Smuzhiyun #define R8A77970_CLK_S1D1 6 19*4882a593Smuzhiyun #define R8A77970_CLK_S1D2 7 20*4882a593Smuzhiyun #define R8A77970_CLK_S1D4 8 21*4882a593Smuzhiyun #define R8A77970_CLK_S2D1 9 22*4882a593Smuzhiyun #define R8A77970_CLK_S2D2 10 23*4882a593Smuzhiyun #define R8A77970_CLK_S2D4 11 24*4882a593Smuzhiyun #define R8A77970_CLK_LB 12 25*4882a593Smuzhiyun #define R8A77970_CLK_CL 13 26*4882a593Smuzhiyun #define R8A77970_CLK_ZB3 14 27*4882a593Smuzhiyun #define R8A77970_CLK_ZB3D2 15 28*4882a593Smuzhiyun #define R8A77970_CLK_DDR 16 29*4882a593Smuzhiyun #define R8A77970_CLK_CR 17 30*4882a593Smuzhiyun #define R8A77970_CLK_CRD2 18 31*4882a593Smuzhiyun #define R8A77970_CLK_SD0H 19 32*4882a593Smuzhiyun #define R8A77970_CLK_SD0 20 33*4882a593Smuzhiyun #define R8A77970_CLK_RPC 21 34*4882a593Smuzhiyun #define R8A77970_CLK_RPCD2 22 35*4882a593Smuzhiyun #define R8A77970_CLK_MSO 23 36*4882a593Smuzhiyun #define R8A77970_CLK_CANFD 24 37*4882a593Smuzhiyun #define R8A77970_CLK_CSI0 25 38*4882a593Smuzhiyun #define R8A77970_CLK_FRAY 26 39*4882a593Smuzhiyun #define R8A77970_CLK_CP 27 40*4882a593Smuzhiyun #define R8A77970_CLK_CPEX 28 41*4882a593Smuzhiyun #define R8A77970_CLK_R 29 42*4882a593Smuzhiyun #define R8A77970_CLK_OSC 30 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */ 45