1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2019 Renesas Electronics Corp. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ 6*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* r8a77961 CPG Core Clocks */ 11*4882a593Smuzhiyun #define R8A77961_CLK_Z 0 12*4882a593Smuzhiyun #define R8A77961_CLK_Z2 1 13*4882a593Smuzhiyun #define R8A77961_CLK_ZR 2 14*4882a593Smuzhiyun #define R8A77961_CLK_ZG 3 15*4882a593Smuzhiyun #define R8A77961_CLK_ZTR 4 16*4882a593Smuzhiyun #define R8A77961_CLK_ZTRD2 5 17*4882a593Smuzhiyun #define R8A77961_CLK_ZT 6 18*4882a593Smuzhiyun #define R8A77961_CLK_ZX 7 19*4882a593Smuzhiyun #define R8A77961_CLK_S0D1 8 20*4882a593Smuzhiyun #define R8A77961_CLK_S0D2 9 21*4882a593Smuzhiyun #define R8A77961_CLK_S0D3 10 22*4882a593Smuzhiyun #define R8A77961_CLK_S0D4 11 23*4882a593Smuzhiyun #define R8A77961_CLK_S0D6 12 24*4882a593Smuzhiyun #define R8A77961_CLK_S0D8 13 25*4882a593Smuzhiyun #define R8A77961_CLK_S0D12 14 26*4882a593Smuzhiyun #define R8A77961_CLK_S1D1 15 27*4882a593Smuzhiyun #define R8A77961_CLK_S1D2 16 28*4882a593Smuzhiyun #define R8A77961_CLK_S1D4 17 29*4882a593Smuzhiyun #define R8A77961_CLK_S2D1 18 30*4882a593Smuzhiyun #define R8A77961_CLK_S2D2 19 31*4882a593Smuzhiyun #define R8A77961_CLK_S2D4 20 32*4882a593Smuzhiyun #define R8A77961_CLK_S3D1 21 33*4882a593Smuzhiyun #define R8A77961_CLK_S3D2 22 34*4882a593Smuzhiyun #define R8A77961_CLK_S3D4 23 35*4882a593Smuzhiyun #define R8A77961_CLK_LB 24 36*4882a593Smuzhiyun #define R8A77961_CLK_CL 25 37*4882a593Smuzhiyun #define R8A77961_CLK_ZB3 26 38*4882a593Smuzhiyun #define R8A77961_CLK_ZB3D2 27 39*4882a593Smuzhiyun #define R8A77961_CLK_ZB3D4 28 40*4882a593Smuzhiyun #define R8A77961_CLK_CR 29 41*4882a593Smuzhiyun #define R8A77961_CLK_CRD2 30 42*4882a593Smuzhiyun #define R8A77961_CLK_SD0H 31 43*4882a593Smuzhiyun #define R8A77961_CLK_SD0 32 44*4882a593Smuzhiyun #define R8A77961_CLK_SD1H 33 45*4882a593Smuzhiyun #define R8A77961_CLK_SD1 34 46*4882a593Smuzhiyun #define R8A77961_CLK_SD2H 35 47*4882a593Smuzhiyun #define R8A77961_CLK_SD2 36 48*4882a593Smuzhiyun #define R8A77961_CLK_SD3H 37 49*4882a593Smuzhiyun #define R8A77961_CLK_SD3 38 50*4882a593Smuzhiyun #define R8A77961_CLK_SSP2 39 51*4882a593Smuzhiyun #define R8A77961_CLK_SSP1 40 52*4882a593Smuzhiyun #define R8A77961_CLK_SSPRS 41 53*4882a593Smuzhiyun #define R8A77961_CLK_RPC 42 54*4882a593Smuzhiyun #define R8A77961_CLK_RPCD2 43 55*4882a593Smuzhiyun #define R8A77961_CLK_MSO 44 56*4882a593Smuzhiyun #define R8A77961_CLK_CANFD 45 57*4882a593Smuzhiyun #define R8A77961_CLK_HDMI 46 58*4882a593Smuzhiyun #define R8A77961_CLK_CSI0 47 59*4882a593Smuzhiyun /* CLK_CSIREF was removed */ 60*4882a593Smuzhiyun #define R8A77961_CLK_CP 49 61*4882a593Smuzhiyun #define R8A77961_CLK_CPEX 50 62*4882a593Smuzhiyun #define R8A77961_CLK_R 51 63*4882a593Smuzhiyun #define R8A77961_CLK_OSC 52 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */ 66