xref: /OK3568_Linux_fs/kernel/include/dt-bindings/clock/r8a7793-cpg-mssr.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright (C) 2015 Renesas Electronics Corp.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h>
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun /* r8a7793 CPG Core Clocks */
12*4882a593Smuzhiyun #define R8A7793_CLK_Z			0
13*4882a593Smuzhiyun #define R8A7793_CLK_ZG			1
14*4882a593Smuzhiyun #define R8A7793_CLK_ZTR			2
15*4882a593Smuzhiyun #define R8A7793_CLK_ZTRD2		3
16*4882a593Smuzhiyun #define R8A7793_CLK_ZT			4
17*4882a593Smuzhiyun #define R8A7793_CLK_ZX			5
18*4882a593Smuzhiyun #define R8A7793_CLK_ZS			6
19*4882a593Smuzhiyun #define R8A7793_CLK_HP			7
20*4882a593Smuzhiyun #define R8A7793_CLK_I			8
21*4882a593Smuzhiyun #define R8A7793_CLK_B			9
22*4882a593Smuzhiyun #define R8A7793_CLK_LB			10
23*4882a593Smuzhiyun #define R8A7793_CLK_P			11
24*4882a593Smuzhiyun #define R8A7793_CLK_CL			12
25*4882a593Smuzhiyun #define R8A7793_CLK_M2			13
26*4882a593Smuzhiyun #define R8A7793_CLK_ADSP		14
27*4882a593Smuzhiyun #define R8A7793_CLK_ZB3			15
28*4882a593Smuzhiyun #define R8A7793_CLK_ZB3D2		16
29*4882a593Smuzhiyun #define R8A7793_CLK_DDR			17
30*4882a593Smuzhiyun #define R8A7793_CLK_SDH			18
31*4882a593Smuzhiyun #define R8A7793_CLK_SD0			19
32*4882a593Smuzhiyun #define R8A7793_CLK_SD2			20
33*4882a593Smuzhiyun #define R8A7793_CLK_SD3			21
34*4882a593Smuzhiyun #define R8A7793_CLK_MMC0		22
35*4882a593Smuzhiyun #define R8A7793_CLK_MP			23
36*4882a593Smuzhiyun #define R8A7793_CLK_SSP			24
37*4882a593Smuzhiyun #define R8A7793_CLK_SSPRS		25
38*4882a593Smuzhiyun #define R8A7793_CLK_QSPI		26
39*4882a593Smuzhiyun #define R8A7793_CLK_CP			27
40*4882a593Smuzhiyun #define R8A7793_CLK_RCAN		28
41*4882a593Smuzhiyun #define R8A7793_CLK_R			29
42*4882a593Smuzhiyun #define R8A7793_CLK_OSC			30
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */
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