1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * r8a7793 clock definition 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 Renesas Electronics Corporation 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A7793_H__ 9*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A7793_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* CPG */ 12*4882a593Smuzhiyun #define R8A7793_CLK_MAIN 0 13*4882a593Smuzhiyun #define R8A7793_CLK_PLL0 1 14*4882a593Smuzhiyun #define R8A7793_CLK_PLL1 2 15*4882a593Smuzhiyun #define R8A7793_CLK_PLL3 3 16*4882a593Smuzhiyun #define R8A7793_CLK_LB 4 17*4882a593Smuzhiyun #define R8A7793_CLK_QSPI 5 18*4882a593Smuzhiyun #define R8A7793_CLK_SDH 6 19*4882a593Smuzhiyun #define R8A7793_CLK_SD0 7 20*4882a593Smuzhiyun #define R8A7793_CLK_Z 8 21*4882a593Smuzhiyun #define R8A7793_CLK_RCAN 9 22*4882a593Smuzhiyun #define R8A7793_CLK_ADSP 10 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* MSTP0 */ 25*4882a593Smuzhiyun #define R8A7793_CLK_MSIOF0 0 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* MSTP1 */ 28*4882a593Smuzhiyun #define R8A7793_CLK_VCP0 1 29*4882a593Smuzhiyun #define R8A7793_CLK_VPC0 3 30*4882a593Smuzhiyun #define R8A7793_CLK_SSP1 9 31*4882a593Smuzhiyun #define R8A7793_CLK_TMU1 11 32*4882a593Smuzhiyun #define R8A7793_CLK_3DG 12 33*4882a593Smuzhiyun #define R8A7793_CLK_2DDMAC 15 34*4882a593Smuzhiyun #define R8A7793_CLK_FDP1_1 18 35*4882a593Smuzhiyun #define R8A7793_CLK_FDP1_0 19 36*4882a593Smuzhiyun #define R8A7793_CLK_TMU3 21 37*4882a593Smuzhiyun #define R8A7793_CLK_TMU2 22 38*4882a593Smuzhiyun #define R8A7793_CLK_CMT0 24 39*4882a593Smuzhiyun #define R8A7793_CLK_TMU0 25 40*4882a593Smuzhiyun #define R8A7793_CLK_VSP1_DU1 27 41*4882a593Smuzhiyun #define R8A7793_CLK_VSP1_DU0 28 42*4882a593Smuzhiyun #define R8A7793_CLK_VSP1_S 31 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* MSTP2 */ 45*4882a593Smuzhiyun #define R8A7793_CLK_SCIFA2 2 46*4882a593Smuzhiyun #define R8A7793_CLK_SCIFA1 3 47*4882a593Smuzhiyun #define R8A7793_CLK_SCIFA0 4 48*4882a593Smuzhiyun #define R8A7793_CLK_MSIOF2 5 49*4882a593Smuzhiyun #define R8A7793_CLK_SCIFB0 6 50*4882a593Smuzhiyun #define R8A7793_CLK_SCIFB1 7 51*4882a593Smuzhiyun #define R8A7793_CLK_MSIOF1 8 52*4882a593Smuzhiyun #define R8A7793_CLK_SCIFB2 16 53*4882a593Smuzhiyun #define R8A7793_CLK_SYS_DMAC1 18 54*4882a593Smuzhiyun #define R8A7793_CLK_SYS_DMAC0 19 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* MSTP3 */ 57*4882a593Smuzhiyun #define R8A7793_CLK_TPU0 4 58*4882a593Smuzhiyun #define R8A7793_CLK_SDHI2 11 59*4882a593Smuzhiyun #define R8A7793_CLK_SDHI1 12 60*4882a593Smuzhiyun #define R8A7793_CLK_SDHI0 14 61*4882a593Smuzhiyun #define R8A7793_CLK_MMCIF0 15 62*4882a593Smuzhiyun #define R8A7793_CLK_IIC0 18 63*4882a593Smuzhiyun #define R8A7793_CLK_PCIEC 19 64*4882a593Smuzhiyun #define R8A7793_CLK_IIC1 23 65*4882a593Smuzhiyun #define R8A7793_CLK_SSUSB 28 66*4882a593Smuzhiyun #define R8A7793_CLK_CMT1 29 67*4882a593Smuzhiyun #define R8A7793_CLK_USBDMAC0 30 68*4882a593Smuzhiyun #define R8A7793_CLK_USBDMAC1 31 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* MSTP4 */ 71*4882a593Smuzhiyun #define R8A7793_CLK_IRQC 7 72*4882a593Smuzhiyun #define R8A7793_CLK_INTC_SYS 8 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* MSTP5 */ 75*4882a593Smuzhiyun #define R8A7793_CLK_AUDIO_DMAC1 1 76*4882a593Smuzhiyun #define R8A7793_CLK_AUDIO_DMAC0 2 77*4882a593Smuzhiyun #define R8A7793_CLK_ADSP_MOD 6 78*4882a593Smuzhiyun #define R8A7793_CLK_THERMAL 22 79*4882a593Smuzhiyun #define R8A7793_CLK_PWM 23 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* MSTP7 */ 82*4882a593Smuzhiyun #define R8A7793_CLK_EHCI 3 83*4882a593Smuzhiyun #define R8A7793_CLK_HSUSB 4 84*4882a593Smuzhiyun #define R8A7793_CLK_HSCIF2 13 85*4882a593Smuzhiyun #define R8A7793_CLK_SCIF5 14 86*4882a593Smuzhiyun #define R8A7793_CLK_SCIF4 15 87*4882a593Smuzhiyun #define R8A7793_CLK_HSCIF1 16 88*4882a593Smuzhiyun #define R8A7793_CLK_HSCIF0 17 89*4882a593Smuzhiyun #define R8A7793_CLK_SCIF3 18 90*4882a593Smuzhiyun #define R8A7793_CLK_SCIF2 19 91*4882a593Smuzhiyun #define R8A7793_CLK_SCIF1 20 92*4882a593Smuzhiyun #define R8A7793_CLK_SCIF0 21 93*4882a593Smuzhiyun #define R8A7793_CLK_DU1 23 94*4882a593Smuzhiyun #define R8A7793_CLK_DU0 24 95*4882a593Smuzhiyun #define R8A7793_CLK_LVDS0 26 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* MSTP8 */ 98*4882a593Smuzhiyun #define R8A7793_CLK_IPMMU_SGX 0 99*4882a593Smuzhiyun #define R8A7793_CLK_VIN2 9 100*4882a593Smuzhiyun #define R8A7793_CLK_VIN1 10 101*4882a593Smuzhiyun #define R8A7793_CLK_VIN0 11 102*4882a593Smuzhiyun #define R8A7793_CLK_ETHER 13 103*4882a593Smuzhiyun #define R8A7793_CLK_SATA1 14 104*4882a593Smuzhiyun #define R8A7793_CLK_SATA0 15 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* MSTP9 */ 107*4882a593Smuzhiyun #define R8A7793_CLK_GPIO7 4 108*4882a593Smuzhiyun #define R8A7793_CLK_GPIO6 5 109*4882a593Smuzhiyun #define R8A7793_CLK_GPIO5 7 110*4882a593Smuzhiyun #define R8A7793_CLK_GPIO4 8 111*4882a593Smuzhiyun #define R8A7793_CLK_GPIO3 9 112*4882a593Smuzhiyun #define R8A7793_CLK_GPIO2 10 113*4882a593Smuzhiyun #define R8A7793_CLK_GPIO1 11 114*4882a593Smuzhiyun #define R8A7793_CLK_GPIO0 12 115*4882a593Smuzhiyun #define R8A7793_CLK_RCAN1 15 116*4882a593Smuzhiyun #define R8A7793_CLK_RCAN0 16 117*4882a593Smuzhiyun #define R8A7793_CLK_QSPI_MOD 17 118*4882a593Smuzhiyun #define R8A7793_CLK_I2C5 25 119*4882a593Smuzhiyun #define R8A7793_CLK_IICDVFS 26 120*4882a593Smuzhiyun #define R8A7793_CLK_I2C4 27 121*4882a593Smuzhiyun #define R8A7793_CLK_I2C3 28 122*4882a593Smuzhiyun #define R8A7793_CLK_I2C2 29 123*4882a593Smuzhiyun #define R8A7793_CLK_I2C1 30 124*4882a593Smuzhiyun #define R8A7793_CLK_I2C0 31 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* MSTP10 */ 127*4882a593Smuzhiyun #define R8A7793_CLK_SSI_ALL 5 128*4882a593Smuzhiyun #define R8A7793_CLK_SSI9 6 129*4882a593Smuzhiyun #define R8A7793_CLK_SSI8 7 130*4882a593Smuzhiyun #define R8A7793_CLK_SSI7 8 131*4882a593Smuzhiyun #define R8A7793_CLK_SSI6 9 132*4882a593Smuzhiyun #define R8A7793_CLK_SSI5 10 133*4882a593Smuzhiyun #define R8A7793_CLK_SSI4 11 134*4882a593Smuzhiyun #define R8A7793_CLK_SSI3 12 135*4882a593Smuzhiyun #define R8A7793_CLK_SSI2 13 136*4882a593Smuzhiyun #define R8A7793_CLK_SSI1 14 137*4882a593Smuzhiyun #define R8A7793_CLK_SSI0 15 138*4882a593Smuzhiyun #define R8A7793_CLK_SCU_ALL 17 139*4882a593Smuzhiyun #define R8A7793_CLK_SCU_DVC1 18 140*4882a593Smuzhiyun #define R8A7793_CLK_SCU_DVC0 19 141*4882a593Smuzhiyun #define R8A7793_CLK_SCU_CTU1_MIX1 20 142*4882a593Smuzhiyun #define R8A7793_CLK_SCU_CTU0_MIX0 21 143*4882a593Smuzhiyun #define R8A7793_CLK_SCU_SRC9 22 144*4882a593Smuzhiyun #define R8A7793_CLK_SCU_SRC8 23 145*4882a593Smuzhiyun #define R8A7793_CLK_SCU_SRC7 24 146*4882a593Smuzhiyun #define R8A7793_CLK_SCU_SRC6 25 147*4882a593Smuzhiyun #define R8A7793_CLK_SCU_SRC5 26 148*4882a593Smuzhiyun #define R8A7793_CLK_SCU_SRC4 27 149*4882a593Smuzhiyun #define R8A7793_CLK_SCU_SRC3 28 150*4882a593Smuzhiyun #define R8A7793_CLK_SCU_SRC2 29 151*4882a593Smuzhiyun #define R8A7793_CLK_SCU_SRC1 30 152*4882a593Smuzhiyun #define R8A7793_CLK_SCU_SRC0 31 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* MSTP11 */ 155*4882a593Smuzhiyun #define R8A7793_CLK_SCIFA3 6 156*4882a593Smuzhiyun #define R8A7793_CLK_SCIFA4 7 157*4882a593Smuzhiyun #define R8A7793_CLK_SCIFA5 8 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */ 160