1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2015 Renesas Electronics Corp. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* r8a7792 CPG Core Clocks */ 12*4882a593Smuzhiyun #define R8A7792_CLK_Z 0 13*4882a593Smuzhiyun #define R8A7792_CLK_ZG 1 14*4882a593Smuzhiyun #define R8A7792_CLK_ZTR 2 15*4882a593Smuzhiyun #define R8A7792_CLK_ZTRD2 3 16*4882a593Smuzhiyun #define R8A7792_CLK_ZT 4 17*4882a593Smuzhiyun #define R8A7792_CLK_ZX 5 18*4882a593Smuzhiyun #define R8A7792_CLK_ZS 6 19*4882a593Smuzhiyun #define R8A7792_CLK_HP 7 20*4882a593Smuzhiyun #define R8A7792_CLK_I 8 21*4882a593Smuzhiyun #define R8A7792_CLK_B 9 22*4882a593Smuzhiyun #define R8A7792_CLK_LB 10 23*4882a593Smuzhiyun #define R8A7792_CLK_P 11 24*4882a593Smuzhiyun #define R8A7792_CLK_CL 12 25*4882a593Smuzhiyun #define R8A7792_CLK_M2 13 26*4882a593Smuzhiyun #define R8A7792_CLK_IMP 14 27*4882a593Smuzhiyun #define R8A7792_CLK_ZB3 15 28*4882a593Smuzhiyun #define R8A7792_CLK_ZB3D2 16 29*4882a593Smuzhiyun #define R8A7792_CLK_DDR 17 30*4882a593Smuzhiyun #define R8A7792_CLK_SD 18 31*4882a593Smuzhiyun #define R8A7792_CLK_MP 19 32*4882a593Smuzhiyun #define R8A7792_CLK_QSPI 20 33*4882a593Smuzhiyun #define R8A7792_CLK_CP 21 34*4882a593Smuzhiyun #define R8A7792_CLK_CPEX 22 35*4882a593Smuzhiyun #define R8A7792_CLK_RCAN 23 36*4882a593Smuzhiyun #define R8A7792_CLK_R 24 37*4882a593Smuzhiyun #define R8A7792_CLK_OSC 25 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */ 40