1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 Cogent Embedded, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A7792_H__ 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A7792_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* CPG */ 10*4882a593Smuzhiyun #define R8A7792_CLK_MAIN 0 11*4882a593Smuzhiyun #define R8A7792_CLK_PLL0 1 12*4882a593Smuzhiyun #define R8A7792_CLK_PLL1 2 13*4882a593Smuzhiyun #define R8A7792_CLK_PLL3 3 14*4882a593Smuzhiyun #define R8A7792_CLK_LB 4 15*4882a593Smuzhiyun #define R8A7792_CLK_QSPI 5 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* MSTP0 */ 18*4882a593Smuzhiyun #define R8A7792_CLK_MSIOF0 0 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* MSTP1 */ 21*4882a593Smuzhiyun #define R8A7792_CLK_JPU 6 22*4882a593Smuzhiyun #define R8A7792_CLK_TMU1 11 23*4882a593Smuzhiyun #define R8A7792_CLK_TMU3 21 24*4882a593Smuzhiyun #define R8A7792_CLK_TMU2 22 25*4882a593Smuzhiyun #define R8A7792_CLK_CMT0 24 26*4882a593Smuzhiyun #define R8A7792_CLK_TMU0 25 27*4882a593Smuzhiyun #define R8A7792_CLK_VSP1DU1 27 28*4882a593Smuzhiyun #define R8A7792_CLK_VSP1DU0 28 29*4882a593Smuzhiyun #define R8A7792_CLK_VSP1_SY 31 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* MSTP2 */ 32*4882a593Smuzhiyun #define R8A7792_CLK_MSIOF1 8 33*4882a593Smuzhiyun #define R8A7792_CLK_SYS_DMAC1 18 34*4882a593Smuzhiyun #define R8A7792_CLK_SYS_DMAC0 19 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* MSTP3 */ 37*4882a593Smuzhiyun #define R8A7792_CLK_TPU0 4 38*4882a593Smuzhiyun #define R8A7792_CLK_SDHI0 14 39*4882a593Smuzhiyun #define R8A7792_CLK_CMT1 29 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* MSTP4 */ 42*4882a593Smuzhiyun #define R8A7792_CLK_IRQC 7 43*4882a593Smuzhiyun #define R8A7792_CLK_INTC_SYS 8 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* MSTP5 */ 46*4882a593Smuzhiyun #define R8A7792_CLK_AUDIO_DMAC0 2 47*4882a593Smuzhiyun #define R8A7792_CLK_THERMAL 22 48*4882a593Smuzhiyun #define R8A7792_CLK_PWM 23 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* MSTP7 */ 51*4882a593Smuzhiyun #define R8A7792_CLK_HSCIF1 16 52*4882a593Smuzhiyun #define R8A7792_CLK_HSCIF0 17 53*4882a593Smuzhiyun #define R8A7792_CLK_SCIF3 18 54*4882a593Smuzhiyun #define R8A7792_CLK_SCIF2 19 55*4882a593Smuzhiyun #define R8A7792_CLK_SCIF1 20 56*4882a593Smuzhiyun #define R8A7792_CLK_SCIF0 21 57*4882a593Smuzhiyun #define R8A7792_CLK_DU1 23 58*4882a593Smuzhiyun #define R8A7792_CLK_DU0 24 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* MSTP8 */ 61*4882a593Smuzhiyun #define R8A7792_CLK_VIN5 4 62*4882a593Smuzhiyun #define R8A7792_CLK_VIN4 5 63*4882a593Smuzhiyun #define R8A7792_CLK_VIN3 8 64*4882a593Smuzhiyun #define R8A7792_CLK_VIN2 9 65*4882a593Smuzhiyun #define R8A7792_CLK_VIN1 10 66*4882a593Smuzhiyun #define R8A7792_CLK_VIN0 11 67*4882a593Smuzhiyun #define R8A7792_CLK_ETHERAVB 12 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* MSTP9 */ 70*4882a593Smuzhiyun #define R8A7792_CLK_GPIO7 4 71*4882a593Smuzhiyun #define R8A7792_CLK_GPIO6 5 72*4882a593Smuzhiyun #define R8A7792_CLK_GPIO5 7 73*4882a593Smuzhiyun #define R8A7792_CLK_GPIO4 8 74*4882a593Smuzhiyun #define R8A7792_CLK_GPIO3 9 75*4882a593Smuzhiyun #define R8A7792_CLK_GPIO2 10 76*4882a593Smuzhiyun #define R8A7792_CLK_GPIO1 11 77*4882a593Smuzhiyun #define R8A7792_CLK_GPIO0 12 78*4882a593Smuzhiyun #define R8A7792_CLK_GPIO11 13 79*4882a593Smuzhiyun #define R8A7792_CLK_GPIO10 14 80*4882a593Smuzhiyun #define R8A7792_CLK_CAN1 15 81*4882a593Smuzhiyun #define R8A7792_CLK_CAN0 16 82*4882a593Smuzhiyun #define R8A7792_CLK_QSPI_MOD 17 83*4882a593Smuzhiyun #define R8A7792_CLK_GPIO9 19 84*4882a593Smuzhiyun #define R8A7792_CLK_GPIO8 21 85*4882a593Smuzhiyun #define R8A7792_CLK_I2C5 25 86*4882a593Smuzhiyun #define R8A7792_CLK_IICDVFS 26 87*4882a593Smuzhiyun #define R8A7792_CLK_I2C4 27 88*4882a593Smuzhiyun #define R8A7792_CLK_I2C3 28 89*4882a593Smuzhiyun #define R8A7792_CLK_I2C2 29 90*4882a593Smuzhiyun #define R8A7792_CLK_I2C1 30 91*4882a593Smuzhiyun #define R8A7792_CLK_I2C0 31 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* MSTP10 */ 94*4882a593Smuzhiyun #define R8A7792_CLK_SSI_ALL 5 95*4882a593Smuzhiyun #define R8A7792_CLK_SSI4 11 96*4882a593Smuzhiyun #define R8A7792_CLK_SSI3 12 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */ 99