1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2013 Ideas On Board SPRL 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A7791_H__ 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A7791_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* CPG */ 10*4882a593Smuzhiyun #define R8A7791_CLK_MAIN 0 11*4882a593Smuzhiyun #define R8A7791_CLK_PLL0 1 12*4882a593Smuzhiyun #define R8A7791_CLK_PLL1 2 13*4882a593Smuzhiyun #define R8A7791_CLK_PLL3 3 14*4882a593Smuzhiyun #define R8A7791_CLK_LB 4 15*4882a593Smuzhiyun #define R8A7791_CLK_QSPI 5 16*4882a593Smuzhiyun #define R8A7791_CLK_SDH 6 17*4882a593Smuzhiyun #define R8A7791_CLK_SD0 7 18*4882a593Smuzhiyun #define R8A7791_CLK_Z 8 19*4882a593Smuzhiyun #define R8A7791_CLK_RCAN 9 20*4882a593Smuzhiyun #define R8A7791_CLK_ADSP 10 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* MSTP0 */ 23*4882a593Smuzhiyun #define R8A7791_CLK_MSIOF0 0 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* MSTP1 */ 26*4882a593Smuzhiyun #define R8A7791_CLK_VCP0 1 27*4882a593Smuzhiyun #define R8A7791_CLK_VPC0 3 28*4882a593Smuzhiyun #define R8A7791_CLK_JPU 6 29*4882a593Smuzhiyun #define R8A7791_CLK_SSP1 9 30*4882a593Smuzhiyun #define R8A7791_CLK_TMU1 11 31*4882a593Smuzhiyun #define R8A7791_CLK_3DG 12 32*4882a593Smuzhiyun #define R8A7791_CLK_2DDMAC 15 33*4882a593Smuzhiyun #define R8A7791_CLK_FDP1_1 18 34*4882a593Smuzhiyun #define R8A7791_CLK_FDP1_0 19 35*4882a593Smuzhiyun #define R8A7791_CLK_TMU3 21 36*4882a593Smuzhiyun #define R8A7791_CLK_TMU2 22 37*4882a593Smuzhiyun #define R8A7791_CLK_CMT0 24 38*4882a593Smuzhiyun #define R8A7791_CLK_TMU0 25 39*4882a593Smuzhiyun #define R8A7791_CLK_VSP1_DU1 27 40*4882a593Smuzhiyun #define R8A7791_CLK_VSP1_DU0 28 41*4882a593Smuzhiyun #define R8A7791_CLK_VSP1_S 31 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* MSTP2 */ 44*4882a593Smuzhiyun #define R8A7791_CLK_SCIFA2 2 45*4882a593Smuzhiyun #define R8A7791_CLK_SCIFA1 3 46*4882a593Smuzhiyun #define R8A7791_CLK_SCIFA0 4 47*4882a593Smuzhiyun #define R8A7791_CLK_MSIOF2 5 48*4882a593Smuzhiyun #define R8A7791_CLK_SCIFB0 6 49*4882a593Smuzhiyun #define R8A7791_CLK_SCIFB1 7 50*4882a593Smuzhiyun #define R8A7791_CLK_MSIOF1 8 51*4882a593Smuzhiyun #define R8A7791_CLK_SCIFB2 16 52*4882a593Smuzhiyun #define R8A7791_CLK_SYS_DMAC1 18 53*4882a593Smuzhiyun #define R8A7791_CLK_SYS_DMAC0 19 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* MSTP3 */ 56*4882a593Smuzhiyun #define R8A7791_CLK_TPU0 4 57*4882a593Smuzhiyun #define R8A7791_CLK_SDHI2 11 58*4882a593Smuzhiyun #define R8A7791_CLK_SDHI1 12 59*4882a593Smuzhiyun #define R8A7791_CLK_SDHI0 14 60*4882a593Smuzhiyun #define R8A7791_CLK_MMCIF0 15 61*4882a593Smuzhiyun #define R8A7791_CLK_IIC0 18 62*4882a593Smuzhiyun #define R8A7791_CLK_PCIEC 19 63*4882a593Smuzhiyun #define R8A7791_CLK_IIC1 23 64*4882a593Smuzhiyun #define R8A7791_CLK_SSUSB 28 65*4882a593Smuzhiyun #define R8A7791_CLK_CMT1 29 66*4882a593Smuzhiyun #define R8A7791_CLK_USBDMAC0 30 67*4882a593Smuzhiyun #define R8A7791_CLK_USBDMAC1 31 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* MSTP4 */ 70*4882a593Smuzhiyun #define R8A7791_CLK_IRQC 7 71*4882a593Smuzhiyun #define R8A7791_CLK_INTC_SYS 8 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* MSTP5 */ 74*4882a593Smuzhiyun #define R8A7791_CLK_AUDIO_DMAC1 1 75*4882a593Smuzhiyun #define R8A7791_CLK_AUDIO_DMAC0 2 76*4882a593Smuzhiyun #define R8A7791_CLK_ADSP_MOD 6 77*4882a593Smuzhiyun #define R8A7791_CLK_THERMAL 22 78*4882a593Smuzhiyun #define R8A7791_CLK_PWM 23 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* MSTP7 */ 81*4882a593Smuzhiyun #define R8A7791_CLK_EHCI 3 82*4882a593Smuzhiyun #define R8A7791_CLK_HSUSB 4 83*4882a593Smuzhiyun #define R8A7791_CLK_HSCIF2 13 84*4882a593Smuzhiyun #define R8A7791_CLK_SCIF5 14 85*4882a593Smuzhiyun #define R8A7791_CLK_SCIF4 15 86*4882a593Smuzhiyun #define R8A7791_CLK_HSCIF1 16 87*4882a593Smuzhiyun #define R8A7791_CLK_HSCIF0 17 88*4882a593Smuzhiyun #define R8A7791_CLK_SCIF3 18 89*4882a593Smuzhiyun #define R8A7791_CLK_SCIF2 19 90*4882a593Smuzhiyun #define R8A7791_CLK_SCIF1 20 91*4882a593Smuzhiyun #define R8A7791_CLK_SCIF0 21 92*4882a593Smuzhiyun #define R8A7791_CLK_DU1 23 93*4882a593Smuzhiyun #define R8A7791_CLK_DU0 24 94*4882a593Smuzhiyun #define R8A7791_CLK_LVDS0 26 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* MSTP8 */ 97*4882a593Smuzhiyun #define R8A7791_CLK_IPMMU_SGX 0 98*4882a593Smuzhiyun #define R8A7791_CLK_MLB 2 99*4882a593Smuzhiyun #define R8A7791_CLK_VIN2 9 100*4882a593Smuzhiyun #define R8A7791_CLK_VIN1 10 101*4882a593Smuzhiyun #define R8A7791_CLK_VIN0 11 102*4882a593Smuzhiyun #define R8A7791_CLK_ETHERAVB 12 103*4882a593Smuzhiyun #define R8A7791_CLK_ETHER 13 104*4882a593Smuzhiyun #define R8A7791_CLK_SATA1 14 105*4882a593Smuzhiyun #define R8A7791_CLK_SATA0 15 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* MSTP9 */ 108*4882a593Smuzhiyun #define R8A7791_CLK_GYROADC 1 109*4882a593Smuzhiyun #define R8A7791_CLK_GPIO7 4 110*4882a593Smuzhiyun #define R8A7791_CLK_GPIO6 5 111*4882a593Smuzhiyun #define R8A7791_CLK_GPIO5 7 112*4882a593Smuzhiyun #define R8A7791_CLK_GPIO4 8 113*4882a593Smuzhiyun #define R8A7791_CLK_GPIO3 9 114*4882a593Smuzhiyun #define R8A7791_CLK_GPIO2 10 115*4882a593Smuzhiyun #define R8A7791_CLK_GPIO1 11 116*4882a593Smuzhiyun #define R8A7791_CLK_GPIO0 12 117*4882a593Smuzhiyun #define R8A7791_CLK_RCAN1 15 118*4882a593Smuzhiyun #define R8A7791_CLK_RCAN0 16 119*4882a593Smuzhiyun #define R8A7791_CLK_QSPI_MOD 17 120*4882a593Smuzhiyun #define R8A7791_CLK_I2C5 25 121*4882a593Smuzhiyun #define R8A7791_CLK_IICDVFS 26 122*4882a593Smuzhiyun #define R8A7791_CLK_I2C4 27 123*4882a593Smuzhiyun #define R8A7791_CLK_I2C3 28 124*4882a593Smuzhiyun #define R8A7791_CLK_I2C2 29 125*4882a593Smuzhiyun #define R8A7791_CLK_I2C1 30 126*4882a593Smuzhiyun #define R8A7791_CLK_I2C0 31 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* MSTP10 */ 129*4882a593Smuzhiyun #define R8A7791_CLK_SSI_ALL 5 130*4882a593Smuzhiyun #define R8A7791_CLK_SSI9 6 131*4882a593Smuzhiyun #define R8A7791_CLK_SSI8 7 132*4882a593Smuzhiyun #define R8A7791_CLK_SSI7 8 133*4882a593Smuzhiyun #define R8A7791_CLK_SSI6 9 134*4882a593Smuzhiyun #define R8A7791_CLK_SSI5 10 135*4882a593Smuzhiyun #define R8A7791_CLK_SSI4 11 136*4882a593Smuzhiyun #define R8A7791_CLK_SSI3 12 137*4882a593Smuzhiyun #define R8A7791_CLK_SSI2 13 138*4882a593Smuzhiyun #define R8A7791_CLK_SSI1 14 139*4882a593Smuzhiyun #define R8A7791_CLK_SSI0 15 140*4882a593Smuzhiyun #define R8A7791_CLK_SCU_ALL 17 141*4882a593Smuzhiyun #define R8A7791_CLK_SCU_DVC1 18 142*4882a593Smuzhiyun #define R8A7791_CLK_SCU_DVC0 19 143*4882a593Smuzhiyun #define R8A7791_CLK_SCU_CTU1_MIX1 20 144*4882a593Smuzhiyun #define R8A7791_CLK_SCU_CTU0_MIX0 21 145*4882a593Smuzhiyun #define R8A7791_CLK_SCU_SRC9 22 146*4882a593Smuzhiyun #define R8A7791_CLK_SCU_SRC8 23 147*4882a593Smuzhiyun #define R8A7791_CLK_SCU_SRC7 24 148*4882a593Smuzhiyun #define R8A7791_CLK_SCU_SRC6 25 149*4882a593Smuzhiyun #define R8A7791_CLK_SCU_SRC5 26 150*4882a593Smuzhiyun #define R8A7791_CLK_SCU_SRC4 27 151*4882a593Smuzhiyun #define R8A7791_CLK_SCU_SRC3 28 152*4882a593Smuzhiyun #define R8A7791_CLK_SCU_SRC2 29 153*4882a593Smuzhiyun #define R8A7791_CLK_SCU_SRC1 30 154*4882a593Smuzhiyun #define R8A7791_CLK_SCU_SRC0 31 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* MSTP11 */ 157*4882a593Smuzhiyun #define R8A7791_CLK_SCIFA3 6 158*4882a593Smuzhiyun #define R8A7791_CLK_SCIFA4 7 159*4882a593Smuzhiyun #define R8A7791_CLK_SCIFA5 8 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */ 162