1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2015 Renesas Electronics Corp. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* r8a7790 CPG Core Clocks */ 12*4882a593Smuzhiyun #define R8A7790_CLK_Z 0 13*4882a593Smuzhiyun #define R8A7790_CLK_Z2 1 14*4882a593Smuzhiyun #define R8A7790_CLK_ZG 2 15*4882a593Smuzhiyun #define R8A7790_CLK_ZTR 3 16*4882a593Smuzhiyun #define R8A7790_CLK_ZTRD2 4 17*4882a593Smuzhiyun #define R8A7790_CLK_ZT 5 18*4882a593Smuzhiyun #define R8A7790_CLK_ZX 6 19*4882a593Smuzhiyun #define R8A7790_CLK_ZS 7 20*4882a593Smuzhiyun #define R8A7790_CLK_HP 8 21*4882a593Smuzhiyun #define R8A7790_CLK_I 9 22*4882a593Smuzhiyun #define R8A7790_CLK_B 10 23*4882a593Smuzhiyun #define R8A7790_CLK_LB 11 24*4882a593Smuzhiyun #define R8A7790_CLK_P 12 25*4882a593Smuzhiyun #define R8A7790_CLK_CL 13 26*4882a593Smuzhiyun #define R8A7790_CLK_M2 14 27*4882a593Smuzhiyun #define R8A7790_CLK_ADSP 15 28*4882a593Smuzhiyun #define R8A7790_CLK_IMP 16 29*4882a593Smuzhiyun #define R8A7790_CLK_ZB3 17 30*4882a593Smuzhiyun #define R8A7790_CLK_ZB3D2 18 31*4882a593Smuzhiyun #define R8A7790_CLK_DDR 19 32*4882a593Smuzhiyun #define R8A7790_CLK_SDH 20 33*4882a593Smuzhiyun #define R8A7790_CLK_SD0 21 34*4882a593Smuzhiyun #define R8A7790_CLK_SD1 22 35*4882a593Smuzhiyun #define R8A7790_CLK_SD2 23 36*4882a593Smuzhiyun #define R8A7790_CLK_SD3 24 37*4882a593Smuzhiyun #define R8A7790_CLK_MMC0 25 38*4882a593Smuzhiyun #define R8A7790_CLK_MMC1 26 39*4882a593Smuzhiyun #define R8A7790_CLK_MP 27 40*4882a593Smuzhiyun #define R8A7790_CLK_SSP 28 41*4882a593Smuzhiyun #define R8A7790_CLK_SSPRS 29 42*4882a593Smuzhiyun #define R8A7790_CLK_QSPI 30 43*4882a593Smuzhiyun #define R8A7790_CLK_CP 31 44*4882a593Smuzhiyun #define R8A7790_CLK_RCAN 32 45*4882a593Smuzhiyun #define R8A7790_CLK_R 33 46*4882a593Smuzhiyun #define R8A7790_CLK_OSC 34 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */ 49